IP Library Granted Patent US 7,760,781
Granted Patent B1
US 7,760,781 · App. 12/150,615 · Granted Jul 20, 2010

Current control mechanism for low voltage applications

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Quick Facts
Patent No.
US 7,760,781
App. No.
12/150,615
Granted
Jul 20, 2010
Kind
B1
Abstract

A current control mechanism for use in low power consumption circuits with limited headroom includes a differential transistor pair from whose collectors a current output is taken. The current output is a function of a reference voltage provided at bases of a reference transistor pair having emitters that are coupled to the bases of the differential pair. The reference voltage is controlled by a pair of control transistors that control current through a load. A pair of tracking transistors can be provided to track supply voltage. A single-ended topology can also be implemented.

Claims (27)

1. A current control circuit comprising:

a differential pair of transistors each having a base, emitter and collector, the emitters of the pair of transistors being coupled together at a common node through which a differential pair current flows, and each collector of the pair of transistors providing an output;

a pair of reference transistors each coupled between a voltage supply and a base of an associated one of the differential pair of transistors, each reference transistor having a reference node at a base thereof;

a current source configured to supply current through each reference node; and

a pair of control transistors each configured to control a voltage of an associated one of the reference nodes by controlling current through a load that is coupled to the associated reference node.

2. The circuit of claim 1 , further comprising a pair of tracking transistors each coupled to an associated one of the reference nodes, the tracking transistors varying current through the reference node based on variations in voltage from the voltage supply.

3. The circuit of claim 1 , wherein at least one of the pairs of transistors is an InGaP device.

4. The circuit of claim 1 , wherein the current source is a current mirror coupled to each reference node.

5. An optoelectronic device driver circuit comprising:

a plurality of differential amplifier stages configured for coupling to an optoelectronic device for driving same in accordance with a modulation signal, at least one of the differential amplifier stages comprising:

a differential pair of transistors each having a base, emitter and collector, the emitters of the pair of transistors being coupled together at a common node through which a differential pair current flows, and each collector of the pair of transistors providing an output;

a pair of reference transistors each coupled between a voltage supply and a base of an associated one of the differential pair of transistors, each reference transistor having a reference node at a base thereof;

a current source configured to supply current through each reference node; and

a pair of control transistors each configured to control a voltage of an associated one of the reference nodes by controlling current through a load that is coupled to the associated reference node.

6. The optoelectronic device driver circuit of claim 5 , further comprising a pair of tracking transistors each coupled to an associated one of the reference nodes, the tracking transistors varying current through the reference node based on variations in voltage from the voltage supply.

7. The optoelectronic device driver circuit of claim 6 , wherein at least one of the pairs of transistors is an InGaP device.

8. The optoelectronic device driver circuit of claim 6 , wherein the current source is a current mirror coupled to each reference node.

9. An optoelectronic system comprising:

a laser diode;

one or more differential amplifier stages connected in cascade such that the ultimate stage is configured for coupling to the laser diode for driving same in accordance with a modulation signal, at least one of the differential amplifier stages comprising:

a differential pair of transistors each having a base, emitter and collector, the emitters of the pair of transistors being coupled together at a common node through which a differential pair current flows, and each collector of the pair of transistors providing an output;

a pair of reference transistors each coupled between a voltage supply and a base of an associated one of the differential pair of transistors, each reference transistor having a reference node at a base thereof;

a current source configured to supply current through each reference node; and a pair of control transistors each configured to control a voltage of an associated one of the reference nodes by controlling current through a load that is coupled to the associated reference node.

10. The system of claim 9 , wherein the at least one of the differential amplifier stages is the penultimate stage.

11. The system of claim 9 , further comprising a pair of tracking transistors each coupled to an associated one of the reference nodes, the tracking transistors varying current through the reference node based on variations in voltage from the voltage supply.

12. The system of claim 9 , wherein at least one of the pairs of transistors is an InGaP device.

13. The system of claim 9 , wherein the current source is a current mirror coupled to each reference node.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Mar 29, 2019
From: JPMORGAN CHASE BANK, N.A.
To: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; CHIPX, INCORPORATED; ENDWAVE CORPORATION; MAGNUM SEMICONDUCTOR, INC.
Reel/Frame 048746/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 4, 2017
From: GIGPEAK, INC.
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 043207/0576 →
RELEASE OF SECURITY INTEREST Recorded Apr 5, 2017
From: SILICON VALLEY BANK
To: GIGPEAK, INC.
Reel/Frame 041856/0100 →
SECURITY AGREEMENT Recorded Apr 5, 2017
From: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; MAGNUM SEMICONDUCTOR, INC.; ENDWAVE CORPORATION; CHIPX, INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 042166/0431 →
CHANGE OF NAME Recorded Feb 9, 2017
From: GIGOPTIX, INC.
To: GIGPEAK, INC.
Reel/Frame 041217/0342 →
AMENDED AND RESTATED INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Apr 6, 2016
From: GIGOPTIX, INC.
To: SILICON VALLEY BANK
Reel/Frame 038369/0552 →