IP Library Granted Patent US 7,586,343
Granted Patent B2
US 7,586,343 · App. 11/800,438 · Granted Sep 8, 2009

Output drive circuit that accommodates variable supply voltages

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Quick Facts
Patent No.
US 7,586,343
App. No.
11/800,438
Granted
Sep 8, 2009
Kind
B2
Abstract

In accordance with the invention, a driver circuit is described that permits a single thin gate oxide process to be utilized where a dual oxide process may normally be necessary. Circuits employing only thin gate oxide devices are used as the design basis for a single product with a single set of tooling and manufacturing process to operate within the same timing specifications for a core voltage output drive as well as for a higher system drive.

Claims (8)

1. A method of driving an output voltage, comprising:

providing a bias voltage to a level shifter that is coupled to provide a gate voltage to a first transistor, the first transistor being coupled between a power supply voltage and an output pad, the bias voltage being an intermediate voltage when the power supply voltage is a high voltage and the bias voltage being a ground voltage when the power supply voltage is a low voltage;

generating a signal in the level shifter that is responsive to an input signal for application as the gate voltage of the first transistor;

providing the bias voltage to a control circuit that is coupled to a gate of a second transistor that is coupled between the first transistor and the output pad;

wherein voltages applied to a gate oxide of the first transistor and a gate oxide of the second transistor do not exceed the low voltage.

2. The method of driving an output voltage as in claim 1 , further including momentarily grounding the bias voltage in a transition of an input voltage from low to high.

3. The method of driving an output voltage as in claim 1 , further including applying a ground to the output pad when a low input signal is provided and charging the output pad when the input signal is a high input signal.

4. The method of driving an output voltage as in claim 1 , further including insuring that voltages applied across gate oxides are lower than design limitations.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Mar 29, 2019
From: JPMORGAN CHASE BANK, N.A.
To: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; CHIPX, INCORPORATED; ENDWAVE CORPORATION; MAGNUM SEMICONDUCTOR, INC.
Reel/Frame 048746/0001 →
SECURITY AGREEMENT Recorded Apr 5, 2017
From: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; MAGNUM SEMICONDUCTOR, INC.; ENDWAVE CORPORATION; CHIPX, INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 042166/0431 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 28, 2017
From: PILLIN, DAVID; LEE, KAR-CHUNG LEO; AU, MARIO FULAM
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 041769/0382 →