Switched-capacitor pipeline stage
View Patent ↗A circuit for an N-bit stage ( 110 i ) of a pipeline ADC having L=2 N levels, the circuit comprising: an operational amplifier ( 420 ); a first feedback capacitor (C f1 ) having a first plate connected to an input of the operational amplifier and a second plate switchably connected on a first clock signal (φ 1 ) to a first input voltage (±V m ) and on a second clock signal (φ 2 ) to an output of the operational amplifier; a second feedback capacitor (C f2 ) having a first plate connected to the input of the operational amplifier and a second plate switchably connected on the first clock signal to a discharge connection and on the second clock signal (φ 2 ) to an output of the operational amplifier; and a plurality of K sampling capacitors (C u ), each sampling capacitor having a first plate connected on the first clock signal to the input of the operational amplifier and a second plate switchably connected on the first clock signal to a second input voltage (V in ) and on the second clock signal to one of a positive and negative reference voltage (+V ref , −V ref ) dependent on a quantized value of an analog input signal (Vm).
1. A method of designing a circuit for an N-bit stage having L=2 N levels of a pipeline ADC, the circuit including:
an operational amplifier;
a first feedback capacitor having a first plate connected to an input of the operational amplifier and a second plate switchably connected on a first clock signal to a first input voltage and on a second clock signal to an output of the operational amplifier;
a second feedback capacitor having a first plate connected to the input of the operational amplifier and a second plate switchably connected on the first clock signal to a discharge connection and on the second clock signal to the output of the operational amplifier; and
a plurality of K sampling capacitors, each sampling capacitor having a first plate connected to the input of the operational amplifier and a second plate switchably connected on the first clock signal to a second input voltage and on the second clock signal to one of a positive and a negative reference voltage dependent on a quantised value of an analog input signal,
the method comprising the steps of:
for a given reference scaling factor H, determining a total capacitance value Cr of the plurality of K sampling capacitors and a capacitance value C f1 of the first feedback capacitor according to a relationship
C
f
1
=
C
r
(
HL
K
-
1
)
;
and
for a given stage gain G, determining a capacitance value C f2 of the second feedback capacitor according to a relationship
C
f
2
=
C
r
-
C
f
1
G
-
C
f
1
.
2. The method of claim 1 wherein the first input voltage signal is equal in magnitude and sign to the second input voltage signal.
3. The method of claim 1 wherein the first input voltage signal is equal in magnitude and opposite in sign to the second input voltage signal.
4. The method of claim 1 wherein K=L−2.
5. The method of claim 1 , further comprising the step of making the circuit according to the design.
6. A circuit for a stage of an N-bit pipeline ADC, the circuit having a design according to claim 1 .
7. A circuit for an N-bit stage having L=2 N levels of a pipeline ADC, the circuit comprising:
an operational amplifier;
a first feedback capacitor having a first plate connected to an input of the operational amplifier and a second plate switchably connected on a first clock signal to a first input voltage and on a second clock signal to an output of the operational amplifier;
a second feedback capacitor having a first plate connected to the input of the operational amplifier and a second plate switchably connected on the first clock signal to a discharge connection and on the second clock signal to the output of the operational amplifier; and
a plurality of K sampling capacitors, each sampling capacitor having a first plate connected to the input of the operational amplifier and a second plate switchably connected on the first clock signal to a second input voltage and on a second clock signal to one of a positive and a negative reference voltage dependent on a quantised value of an analog input signal,
wherein the second input voltage is of equal magnitude and opposite sign to the first input voltage.
8. The circuit according to claim 7 wherein a total capacitance value C r of the plurality of K sampling capacitors is related to a capacitance value C f1 of the first feedback capacitor by the relationship
C
f
1
=
C
r
(
HL
K
-
1
)
,
where H is a reference scaling factor of the circuit, and wherein a capacitance value C f2 of the second feedback capacitor is related to the capacitance value of the first feedback capacitor and a total capacitance value of the plurality of K sampling capacitors according to a relationship
C
f
2
=
C
r
-
C
f
2
G
-
C
f
1
,
where G is a stage gain of the circuit.
9. The circuit according to claim 7 wherein K=L−2.
10. A circuit for an N-bit stage having L=2 N levels of a pipeline ADC, the circuit comprising:
an operational amplifier;
a first feedback capacitor having a first plate connected to a non-inverting input of the operational amplifier and a second plate switchably connected on a first clock signal to a first input voltage and on a second clock signal to an inverting output of the operational amplifier;
a second feedback capacitor having a first plate connected to the non-inverting input of the operational amplifier and a second plate switchably connected on the first clock signal to a discharge connection and on the second clock signal to the inverting output of the operational amplifier;
a first plurality of K sampling capacitors, each sampling capacitor having a first plate connected to the non-inverting input of the operational amplifier and a second plate switchably connected on the first clock signal to a second input voltage and on a second clock signal to one of a positive and negative reference voltage dependent on a quantised value of an analog input signal;
a third feedback capacitor having a first plate connected to an inverting input of the operational amplifier and a second plate switchably connected on the first clock signal to the second input voltage and on a second clock signal to a non-inverting output of the operational amplifier;
a fourth feedback capacitor having a first plate connected to the inverting input of the operational amplifier and a second plate switchably connected on the first clock signal to the discharge connection and on the second clock signal to the non-inverting output of the operational amplifier; and
a second plurality of K sampling capacitors, each sampling capacitor having a first plate connected to the inverting input of the operational amplifier and a second plate switchably connected on the first clock signal to the first input voltage and on a second clock signal to one of a positive and a negative reference voltage dependent on a quantised value of an analog input signal,
wherein the second input voltage is of equal magnitude and opposite sign to the first input voltage.