Ripple counter circuits in integrated circuit devices having fast terminal count capability and methods of operating the same

1. An integrated circuit device comprising:

a terminal count circuit configured to mask selected unstable counter bits generated by a ripple counter circuit using an indication that a terminal state of the ripple counter circuit has been reached, wherein the terminal count circuit comprises a combinatorial circuit having a first input electrically coupled to an output of the ripple counter circuit and second input electrically coupled to a clock delayed terminal count indication, the combinatorial circuit further comprising an output that indicates the non-terminal state, wherein a propagation delay associated with the combinatorial circuit is less than the one clock period.

2. A circuit according to claim 1 wherein the counter bits stabilize in an initial state of the ripple counter circuit.

3. A circuit according to claim 1 wherein the counter bits comprise upper counter bits that are unstable for more than one clock period after a clock edge used to increment the ripple counter circuit.

4. A circuit according to claim 1 wherein the terminal count circuit further comprises:

a combinatorial circuit configured to de-activate the indication that the terminal state has been reached by masking the state of the counter bits using the indication.

5. A circuit according to claim 4 wherein the combinatorial circuit comprises:

a first combinatorial gate electrically coupled to the indication that the terminal state has been reached and configured to de-activate the indication that the terminal state has been reached; and

a second combinatorial gate electrically coupled to the indication that the terminal state has been reached and configured to mask the state of the counter bits using the indication.

6. A circuit in an integrated circuit device comprising:

a terminal count circuit configured to indicate a terminal state for a high frequency ripple counter circuit less than one high frequency clock period after the ripple counter circuit enters the terminal state;

wherein the terminal count circuit is further configured to load the ripple counter circuit with an arbitrary initial state responsive to a high frequency clock edge that is immediately subsequent in time to the indication of the terminal state;

wherein the terminal count circuit is further configured to change the indication of the terminal state to a non-terminal state responsive to the high frequency clock edge that is immediately subsequent in time to the clock edge in which the ripple counter circuit enters the terminal state; and

wherein the terminal count circuit comprises a combinatorial circuit having an input electrically coupled to an output of the ripple counter circuit and a clock delayed terminal count indication and having an output that indicates the non-terminal state, wherein a propagation delay associated with the combinatorial circuit is less than the one clock period.

7. A circuit in an integrated circuit device comprising:

a terminal count circuit configured to indicate a terminal state for a high frequency ripple counter circuit less than one high frequency clock period after the ripple counter circuit enters the terminal state;

wherein the terminal count circuit comprises a combinatorial circuit having an input electrically coupled to an output of the ripple counter circuit and having an output that indicates the terminal state, wherein a propagation delay associated with the combinatorial circuit is less than the one high frequency clock period;

wherein the combinatorial circuit comprises a first combinatorial circuit, further comprising:

a second combinatorial circuit having an input electrically coupled to an output of the ripple counter circuit other than a least significant output thereof and a clock delayed terminal count indication and having an output electrically coupled to the input of the first combinatorial circuit, wherein a propagation delay associated with the second combinatorial circuit is greater than the propagation delay associated with the first combinatorial circuit.

8. A circuit according to claim 7 wherein the output of the ripple counter circuit other than the least significant bit output thereof comprises at least one upper bit of the ripple counter circuit.

9. A circuit according to claim 8 wherein the least significant output comprises a bit of the ripple counter circuit that remains stable for at least one period after a clock edge that is immediately subsequent in time to indication of the terminal state.

10. A method of controlling a high frequency ripple counter circuit comprising:

counting clock transitions from an arbitrary initial state to a terminal state of the counter circuit to generate an indication that the terminal state has been reached based on counter bits associated with the clock transitions;

indicating that the terminal state has been reached based on the counter bits;

re-loading the counter circuit with the arbitrary initial state; and

masking the counter bits to de-activate the indication that the terminal state has been reached by indicating a non-terminal state to the counter circuit with an output of a combinatorial circuit in a time that is less than or equal to one clock period used to operate the counter circuit measured from a time at which a terminal state indication is provided to the combinatorial circuit to a time at which the non-terminal state is indicated.