Impedance-matched output driver circuits having linear characteristics and enhanced coarse and fine tuning control
View Patent ↗Impedance-matched output driver circuits include a first totem pole driver stage and a second totem pole driver stage. The first totem pole driver stage includes at least one PMOS pull-up transistor and at least one NMOS pull-down transistor therein that are responsive to a first pull-up signal and a first pull-down signal, respectively. The second totem pole driver stage has at least one NMOS pull-up transistor and at least one PMOS pull-down transistor therein that are responsive to a second pull-up signal and second pull-down signal, respectively. The linearity of the output driver circuit is enhanced by including a first resistive element that extends between the first and second totem pole driver stages. The first resistive element has a first terminal, which is electrically coupled to drain terminals of the at least one PMOS pull-up transistor and the at least one NMOS pull-down transistor in the first totem pole driver stage, and a second terminal, which is electrically coupled to source terminals of the at least one NMOS pull-up transistor and the at least one PMOS pull-down transistor in the second totem pole driver stage.
1. An output driver circuit, comprising:
a first totem pole driver stage having at least one PMOS pull-up transistor and at least one NMOS pull-down transistor therein that are responsive to a first pull-up signal and a first pull-down signal, respectively;
a second totem pole driver stage having at least one NMOS pull-up transistor and at least one PMOS pull-down transistor therein that are responsive to a second pull-up signal and second pull-down signal, respectively; and
a first resistive element having a first terminal that is electrically coupled to drain terminals of the at least one PMOS pull-up transistor and the at least one NMOS pull-down transistor and a second terminal that is electrically coupled to source terminals of the at least one NMOS pull-up transistor and the at least one PMOS pull-down transistor.
2. The driver circuit of claim 1 , wherein the first and second pull-up signals are complementary signals; and wherein the first and second pull-down signals are complementary signals.
3. The driver circuit of claim 1 , wherein the drain terminals of the at least one PMOS pull-up transistor and the at least one NMOS pull-down transistor are electrically connected together at a first output node.
4. The driver circuit of claim 3 , wherein the source terminals of the at least one NMOS pull-up transistor and the at least one PMOS pull-down transistor are electrically connected together at a second output node.
5. The driver circuit of claim 4 , further comprising a second resistive element that is electrically connected between an output terminal of the driver circuit and the second output node.
6. The driver circuit of claim 5 , wherein a resistance of the second resistive element is less than a resistance of the first resistive element.
7. The driver circuit of claim 1 , wherein said second totem pole driver stage comprises:
a normally-on PMOS pull-up transistor having a drain terminal electrically connected to a drain terminal of the at least one NMOS pull-up transistor; and
a normally-on NMOS pull-down transistor having a drain terminal electrically connected to a drain terminal of the at least one PMOS pull-down transistor.
8. The driver circuit of claim 1 , wherein said at least one PMOS pull-up transistor comprises:
a coarsely tuned array of binary weighted PMOS pull-up transistors in parallel with a finely tuned array of non-binary weighted PMOS pull-up transistors.
9. The driver circuit of claim 8 , wherein said at least one NMOS pull-down transistor comprises:
a coarsely tuned array of binary weighted NMOS pull-down transistors in parallel with a finely tuned array of non-binary weighted NMOS pull-down transistors.
10. The driver circuit of claim 1 , wherein said at least one NMOS pull-up transistor comprises:
a coarsely tuned array of binary weighted NMOS pull-up transistors in parallel with a finely tuned array of non-binary weighted NMOS pull-up transistors.
11. The driver circuit of claim 10 , wherein said at least one PMOS pull-down transistor comprises:
a coarsely tuned array of binary weighted PMOS pull-down transistors in parallel with a finely tuned array of non-binary weighted PMOS pull-down transistors.
12. The driver circuit of claim 11 , wherein said second totem pole driver stage comprises:
a normally-on PMOS pull-up transistor having a drain terminal electrically connected to a drain terminal of the at least one NMOS pull-up transistor; and
a normally-on NMOS pull-down transistor having a drain terminal electrically connected to a drain terminal of the at least one PMOS pull-down transistor.
13. The driver circuit of claim 1 , wherein said first resistive element has a resistance in a range from between about 5 ohms and about 15 ohms.
14. An output driver circuit, comprising:
a first totem pole driver stage having at least one PMOS pull-up transistor and at least one NMOS pull-down transistor therein that are responsive to a first pull-up signal and a first pull-down signal, respectively;
a second totem pole driver stage having at least one NMOS pull-up transistor and at least one PMOS pull-down transistor therein that are responsive to a second pull-up signal and second pull-down signal, respectively; and
a first resistive element having a resistance value in a range from between about 0 ohms and about 20 ohms, said first resistive element having a first terminal that is electrically coupled to drain terminals of the at least one PMOS pull-up transistor and the at least one NMOS pull-down transistor and a second terminal that is electrically coupled to source terminals of the at least one NMOS pull-up transistor and the at least one PMOS pull-down transistor;
wherein said at least one PMOS pull-up transistor comprises:
a coarsely tuned array of binary weighted PMOS pull-up transistors in parallel with a finely tuned array of non-binary weighted PMOS pull-up transistors; and
wherein said at least one NMOS pull-down transistor comprises:
a coarsely tuned array of binary weighted NMOS pull-down transistors in parallel with a finely tuned array of non-binary weighted NMOS pull-down transistors.
15. The driver circuit of claim 14 , wherein said at least one NMOS pull-up transistor comprises a coarsely tuned array of binary weighted NMOS pull-up transistors in parallel with a finely tuned array of non-binary weighted NMOS pull-up transistors.
16. An output driver circuit, comprising:
a first totem pole driver stage having at least one PMOS pull-up transistor and at least one NMOS pull-down transistor therein that are responsive to a first pull-up signal and a first pull-down signal, respectively, said at least one PMOS pull-up transistor comprising a coarsely tuned array of binary weighted PMOS pull-up transistors in parallel with a finely tuned array of non-binary weighted PMOS pull-up transistors;
a second totem pole driver stage having at least one NMOS pull-up transistor and at least one PMOS pull-down transistor therein that are responsive to a second pull-up signal and second pull-down signal, respectively, said at least one NMOS pull-up transistor comprising a coarsely tuned array of binary weighted NMOS pull-up transistors in parallel with a finely tuned array of non-binary weighted NMOS pull-up transistors; and
a first resistive element having a resistance value in a range from between about 0 ohms and about 20 ohms, said first resistive element having a first terminal that is electrically coupled to drain terminals of the at least one PMOS pull-up transistor and the at least one NMOS pull-down transistor and a second terminal that is electrically coupled to source terminals of the at least one NMOS pull-up transistor and the at least one PMOS pull-down transistor.
17. The driver circuit of claim 16 , wherein a pair of PMOS pull-up transistors in the finely tuned array of non-binary weighted PMOS pull-up transistors have widths equal to: W+nβ and W+(n+1)β, where n is a positive integer, β is a positive number, W>4 μm and nβ<W.
18. The driver circuit of claim 17 , wherein a plurality of PMOS pull-up transistors in the coarsely tuned array of binary weighted PMOS pull-up transistors have widths equal to: W, 2 W and 4 W.
19. An integrated circuit device, comprising:
a first pull-up path having at least one PMOS pull-up transistor therein that is responsive to a first pull-up signal;
a second pull-up path having at least one NMOS pull-up transistor therein that is responsive to a second pull-up signal; and
a first resistive element having a first terminal that is electrically coupled to a drain terminal of the at least one PMOS pull-up transistor and a second terminal that is electrically coupled to a source terminal of the at least one NMOS pull-up transistor;
wherein said at least one PMOS pull-up transistor comprises:
a coarsely tuned array of binary weighted PMOS pull-up transistors in parallel with a finely tuned array of non-binary weighted PMOS pull-up transistors; and
wherein said at least one NMOS pull-up transistor comprises:
a coarsely tuned array of binary weighted NMOS pull-up transistors in parallel with a finely tuned array of non-binary weighted NMOS pull-up transistors.
20. An integrated circuit device, comprising:
a first pull-down path having at least one NMOS pull-down transistor therein that is responsive to a first pull-down signal;
a second pull-down path having at least one PMOS pull-down transistor therein that is responsive to a second pull-down signal; and
a first resistive element having a first terminal that is electrically coupled to a drain terminal of the at least one NMOS pull-down transistor and a second terminal that is electrically coupled to a source terminal of the at least one PMOS pull-down transistor;
wherein said at least one NMOS pull-down transistor comprises:
a coarsely tuned array of binary weighted NMOS pull-down transistors in parallel with a finely tuned array of non-binary weighted NMOS pull-down transistors; and
wherein said at least one PMOS pull-down transistor comprises:
a coarsely tuned array of binary weighted PMOS pull-down transistors in parallel with a finely tuned array of non-binary weighted PMOS pull-down transistors.
21. An output driver circuit, comprising:
a first totem pole driver stage having at least one PMOS pull-up transistor and at least one NMOS pull-down transistor therein that are responsive to a first pull-up signal and a first pull-down signal, respectively; and
a second totem pole driver stage having at least one NMOS pull-up transistor and at least one PMOS pull-down transistor therein that are responsive to a second pull-up signal and second pull-down signal, respectively;
wherein said at least one PMOS pull-up transistor comprises:
a coarsely tuned array of binary weighted PMOS pull-up transistors in parallel with a finely tuned array of non-binary weighted PMOS pull-up transistors; and
wherein said at least one NMOS pull-down transistor comprises:
a coarsely tuned array of binary weighted NMOS pull-down transistors in parallel with a finely tuned array of non-binary weighted NMOS pull-down transistors.