Dual-coupled phase-locked loops for clock and packet-based synchronization

1. An integrated circuit device, comprising:

a pair of coupled phase-locked loops including a first phase-locked loop responsive to a first clock and a second phase-locked loop configured to track the first clock through the first phase-locked loop when said second phase-locked loop is disposed in a holdover mode of operation and in a locked mode of operation, said first phase-locked loop comprising a first loop filter and a first oscillator responsive to a first output signal generated by the first loop filter and said second phase-locked loop comprising a second loop filter responsive to a second output signal generated by the first loop filter;

wherein the first loop filter comprises a low-pass filter; and

wherein said first phase-locked loop is configured to support a first programmable mode whereby the first and second output signals generated by the first loop filter are equivalent and a second programmable mode whereby the second output signal is generated by the low-pass filter but the first output signal is not.

2. The integrated circuit device of claim 1 , wherein the first oscillator is a digitally-controlled oscillator; and wherein said second phase-locked loop comprises a second digitally-controlled oscillator responsive to an output signal generated by the second loop filter.

3. A Synchronous Ethernet (SyncE) network device, comprising:

a pair of phase-locked loops including a first phase-locked loop responsive to a SyncE input clock and a second phase-locked loop coupled to the first phase-locked loop, said second phase-locked loop configured to be simultaneously lockable to both the SyncE input clock via the first phase-locked loop and an IEEE 1588 packet stream during a locked mode of operation and lockable to the SyncE input clock during a holdover mode of operation that is triggered in response to a failure of the IEEE 1588 packet stream.

4. The network device of claim 3 , wherein the first phase-locked loop comprises a first loop filter and a first digitally-controlled oscillator; and wherein the first loop filter comprises selection circuitry configured to selectively provide a second loop filter within the second phase-locked loop with the same frequency offset provided to the first digitally-controlled oscillator when disposed in a first selection state.

5. The network device of claim 4 , wherein the selection circuitry is further configured to selectively provide the second loop filter with a long term frequency offset of the first phase-locked loop when disposed in a second selection state.

6. The network device of claim 5 , wherein the first phase-locked loop comprises a low pass filter configured to receive the long term frequency offset of the first phase-locked loop; and wherein the selection circuitry is further configured to selectively provide the second loop filter with a post-filtered frequency offset from an output of the low pass filter when disposed in a third selection state.

7. The network device of claim 3 , wherein the second phase-locked loop comprises a phase detector, a loop filter and selection circuitry electrically coupled to the phase detector and the loop filter; said selection circuitry configured to selectively pass a phase offset signal from an output of the phase detector to an input of the loop filter when disposed in a first selection state and pass phase information associated with the IEEE 1588 packet stream to the input of the loop filter when disposed in a second selection state.

8. The network device of claim 7 , wherein the phase information associated with the IEEE 1588 packet stream is received at a serial interface of the network device.

9. The network device of claim 7 , wherein said second phase-locked loop is configured to generate a one-pulse-per-second (1PPS) timing signal at an output thereof, which is also fed back to a first input of the phase detector.

10. The network device of claim 9 , wherein said second phase-locked loop comprises a divider configured to generate the 1PPS timing signal in response to an output clock signal; and wherein the phase information associated with the IEEE 1588 packet stream is received at a serial interface of the network device and provided to an input of the divider.