Method and apparatus for a low power AC On-Die-Termination (ODT) circuit

1. A circuit on an integrated circuit comprising:

a first resistor having an input and an output, said first resistor input coupled to receive an input;

a first n-channel transistor having a drain, a gate, and a source, said first n-channel gate connected to said first resistor input, and said first n-channel drain connected to said first resistor output;

a second resistor having an input and an output, said second resistor input connected to said first n-channel transistor source;

a second n-channel transistor having a drain, a gate, and a source, said second n-channel transistor drain connected to said second resistor output;

a first p-channel transistor having a source, a gate, and a drain, said first p-channel transistor gate connected to said first resistor input, and said first p-channel transistor drain connected to said first resistor output;

a third resistor having an input and an output, said third resistor input connected to said first p-channel transistor source; and

a second p-channel transistor having a source, a gate, and a drain, said second p-channel transistor drain connected to said third resistor output.

2. The circuit of claim 1 further comprising:

a third n-channel transistor having a drain, a gate, and a source, said third n-channel transistor source connected to said second n-channel transistor source; and

a fourth resistor having an input and an output, said fourth resistor input connected to said second resistor input, and said fourth resistor output connected to said third n-channel transistor drain.

3. The circuit of claim 2 further comprising:

a third p-channel transistor having a source, a gate, and a drain, said third p-channel transistor source connected to said second p-channel transistor source; and

a fifth resistor having an input and an output, said fifth resistor input connected to said third resistor input, and said fifth resistor output connected to said third p-channel transistor drain.

4. The circuit of claim 3 further comprising:

a fourth n-channel transistor having a drain, a gate, and a source, said fourth n-channel transistor source connected to said second n-channel transistor source; and

a sixth resistor having an input and an output, said sixth resistor input connected to said second resistor input, and said sixth resistor output connected to said fourth n-channel transistor drain.

5. The circuit of claim 4 further comprising:

a fourth p-channel transistor having a source, a gate, and a drain, said fourth p-channel transistor source connected to said second p-channel transistor source; and

a seventh resistor having an input and an output, said seventh resistor input connected to said third resistor input, and said seventh resistor output connected to said fourth p-channel transistor drain.

6. The circuit of claim 5 further comprising:

a fifth n-channel transistor having a drain, a gate, and a source, said fifth n-channel transistor source connected to said second n-channel transistor source; and

an eighth resistor having an input and an output, said eighth resistor input connected to said second resistor input, and said eighth resistor output connected to said fifth n-channel transistor drain.

7. The circuit of claim 6 further comprising:

a fifth p-channel transistor having a source, a gate, and a drain, said fifth p-channel transistor source connected to said second p-channel transistor source; and

a ninth resistor having an input and an output, said ninth resistor input connected to said third resistor input, and said ninth resistor output connected to said fifth p-channel transistor drain.

8. The circuit of claim 1 further comprising a first capacitor having an input and an output, said first capacitor input connected to said first resistor input, and said first capacitor output connected to said second n-channel transistor source.

9. The circuit of claim 8 further comprising a second capacitor having an input and an output, said second capacitor input connected to said first resistor output, and said second capacitor output connected to said second n-channel transistor source.

10. The circuit of claim 1 further comprising a second capacitor having an input and an output, said second capacitor input connected to said first resistor output, and said second capacitor output connected to said second n-channel transistor source.

11. A method comprising using an alternating current (AC) on-die-termination (ODT) for a receive and using a degeneration circuit to reduce gm variation in one or more transistors.

12. The method of claim 11 further comprising using a calibration circuit to balance p-channel metal oxide semiconductor and n-channel metal oxide semiconductor variation.

13. The method of claim 12 further comprising using said calibration circuit to build a voltage reference.

14. The method of claim 13 wherein said voltage reference is one-half of a supply voltage.

15. An apparatus comprising:

means for receiving a double data rate memory output at a receiver input on an integrated circuit; and

means for alternating current electrically termination said receiver input to provide a substantially same impedance as a passive electrical termination;

means for using a plurality of resistively connected n-channel transistors to calibrate a first n-channel transistor; and

means for using a plurality of resistively connected p-channel transistors to calibrate a first p-channel transistor.

16. The apparatus of claim 15 further comprising means for producing an output from said receiver input selected from the group consisting of: using said receiver input, using an output derived from said receiver input, and using a differential signal consisting of an output derived from said receiver input and a reference voltage.