Multi-bank integrated circuit memory devices having high-speed memory access timing

1. An integrated circuit memory device, comprising:

a semiconductor chip having a memory core therein and at least N bond pads thereon, said memory core configured to support a xN burst-M write mode of operation at QDR and/or DDR rates and further configured to support one-to-one mapping between burst-M write data received at each of the N bond pads and corresponding ones of N memory blocks in said memory core during the xN burst-M write mode of operation, where N is an integer greater than four and M is an integer greater than one.

2. The memory device of claim 1 , wherein N is at least eighteen and M is greater than two.

3. The memory device of claim 1 , wherein the memory core comprises a plurality of UP and DOWN memory slices arranged side-by-side in an alternating UP and DOWN sequence.

4. The memory device of claim 3 , wherein the one-to-one mapping precludes write data transfers across boundaries extending between the plurality of UP and DOWN memory slices during the xN burst-M write mode of operation.

5. The memory device of claim 3 , further comprising a plurality of bond pad multiplexing cells at each end of the plurality of UP and DOWN memory slices.

6. The memory device of claim 5 , wherein a first of the plurality of bond pad multiplexing cells comprises an input data routing logic circuit and an output data routing logic circuit; and wherein said output data routing logic circuit is configured to receive read data from a corresponding one of the plurality of UP and DOWN memory slices and further configured to receive data directly from the input data routing logic circuit.

7. The memory device of claim 5 , wherein a first one of the plurality of bond pad multiplexing cells comprises:

first bond pad that is active as a data input pad during a separate IO mode of operation and is inactive during a common IO mode of operation; and

a second bond pad that is active as a data output pad during separate and common IO modes of operation and active as a data input pad during the common IO mode of operation.

8. The memory device of claim 3 , wherein the plurality of UP and DOWN memory slices are configured to support all combinations of xN, x2N and x4N DDR and QDR write modes of operation.

9. The memory device of claim 1 , wherein the N memory blocks include:

a first memory block configured so that only write data received at a corresponding first one of the N bond pads can be stored in the first memory block during the xN burst-M write mode of operation and no other ones of the N memory blocks are configured to store data received from the first one of the N bond pads during the xN burst-M write mode of operation; and

a second memory block configured so that only write data received at a corresponding second one of the N bond pads can be stored in the second memory block during the xN burst-M write mode of operation and no other ones of the N memory blocks are configured to store data received from the second one of the N bond pads during the xN burst-M write mode of operation.

10. The memory device of claim 9 , wherein the xN burst-M write mode of operation is a xN burst-4 write mode of operation.

11. The memory device of claim 1 , wherein the memory core comprises a plurality of multi-bank memory blocks configured to receive write data from the N bond pads, said plurality of multi-bank memory blocks comprising:

a first multi-bank memory block configured to support a first write operating mode wherein all banks within the first multi-bank memory block only store data received from a first one of the N bond pads and no banks within any other ones of said plurality of multi-bank memory blocks store data received from the first one of the N bond pads; and

a second multi-bank memory block configured to support the first write operating mode wherein all banks within the second multi-bank memory block only store data received from a second one of the N bond pads and no banks within any other ones of said plurality of multi-bank memory blocks store data received from the second one of the N bond pads.

12. An integrated circuit memory device, comprising:

a semiconductor chip having a memory core therein and at least 4N bond pads thereon, said semiconductor chip configured to support a plurality of write modes of operation including at least a xN burst-M QDR write mode of operation, a xN burst-M DDR write mode of operation, a x2N burst-M QDR write mode of operation, a x2N burst-M DDR write mode of operation, a x4N burst-M QDR write mode of operation and a x4N burst-M DDR write mode of operation, where N is an integer greater than four and M is an integer greater than one.

13. The memory device of claim 12 , wherein the plurality of write modes of operation supported by said semiconductor chip also include a xN burst-2M write mode of operation, a x2N burst-2M write mode of operation and a x4N burst-2M write mode of operation.

14. The memory device of claim 13 , wherein said semiconductor chip is responsive to a plurality of address bits, which operate to select a designated write mode of operation from the plurality of write modes of operation.

15. The memory device of claim 8 , wherein none of the xN, x2N and x4N DDR and QDR write modes of operation support data transfers across boundaries extending between the plurality of UP and DOWN memory slices.

16. The memory device of claim 15 , wherein each of the xN, x2N and x4N DDR and QDR write modes are burst-2 or burst-4 write modes.

17. The memory device of claim 16 , wherein each of the plurality of UP and DOWN memory slices is configurable in quarters during a x4N burst-4 write mode of operation and configurable in halves during a x4N burst-2 write mode of operation.