DDR memory system for measuring a clock signal by identifying a delay value corresponding to a changed logic state during clock signal transitions
View Patent ↗Circuits for measuring a clock signal include a variable digital delay line that is configured to delay the clock signal by variable amounts in response to variable values of a digital control word that are applied thereto, to produce a variably delayed clock signal. A capture stage is responsive to the variably delayed clock signal and to the clock signal to capture a logic state of the variably delayed clock signal during transitions of the clock signal. A controller is configured to generate the variable values of the digital control word that are applied to the variable digital delay line and to identify a value of the digital control word in response to the capture stage capturing a change in the logic state of the variably delayed clock signal during a transition of the clock signal. Related methods and memory devices are also described.
1. A double data rate memory system comprising:
a double data rate memory that is responsive to a clock signal and is configured to generate read data and a read data strobe signal;
a clocked read data latch that is responsive to the read data;
a first variable digital delay line that is configured to delay the read data strobe signal in response to a digital delay control signal and to clock the clocked read data latch with the read data strobe signal that is delayed;
a clock period measurement system that is responsive to the clock signal to generate a delay measurement value; and
an adjustment system that is responsive to the delay measurement value and is configured to adjust the delay measurement value to produce the digital delay control signal;
wherein the clock period measurement system comprises:
a second variable digital delay line that is coupled to the clock signal and is responsive to a digital control word;
a flip-flop that is responsive to the second variable digital delay line and is clocked by a complement of the clock signal; and
a controller that is responsive to the flip-flop and is configured to cycle the digital control word and to identify a value of the digital control word responsive to the flip-flop changing state to provide the delay measurement value.
2. A system according to claim 1 further comprising:
a metastability filtering stage that is responsive to the flip-flop and is configured to reduce metastability in the change in the logic state of the variably delayed clock signal during a transition of the clock signal that is captured by the flip-flop, the controller being responsive to the metastability filtering stage.
3. A system according to claim 1 wherein the flip-flop is a first flip-flop, the system further comprising:
a second flip-flop that is responsive to the first flip-flop and is clocked by the complement of the clock signal;
wherein the controller is responsive to the second flip-flop and is configured to cycle through values of the digital control word and to identify a value of the digital control word responsive to the second flip-flop changing state.
4. A system according to claim 1 wherein the controller is configured to repeatedly cycle through at least a subset of the values of the digital control word, by sequentially increasing from a minimum value and/or sequentially decreasing from a maximum value.
5. A system according to claim 1 wherein the controller is further configured to post-process the value of the digital control word that is identified.
6. A system according to claim 1 wherein the controller is further configured to average a plurality of values of the digital control word that are identified.
7. A system according to claim 1 wherein the first and second variable digital delay lines comprise a same circuit configuration.