Method and apparatus for DQS postamble detection and drift compensation in a double data rate (DDR) physical interface

1. Circuitry for reading from a double data rate type memory, said circuitry comprising:

control logic;

a first bi-directional input/output interface (I/O) configured to be coupled to a data bus of a double data rate type memory and to receive therefrom a data transmission having a duration selected by said control logic;

a second bi-directional input/output interface (I/O) configured to be coupled to a data strobe line of said double data rate type memory;

a gate coupled to said second bi-directional input/output interface configured for controlling the duration of a data strobe signal received along said data strobe line in response to a data strobe masking gating signal; and

a data strobe masking gating signal modifier receiving from said control logic an expected data receipt duration indicating signal and an extent of delay indicating signal and applying to said expected data receipt duration indicating signal a variable time delay based at least in part on said extent of delay indicating signal such as to center said expected data receipt duration indicating signal about the midpoint of said duration of said data transmission.

2. Circuitry for reading from a double data rate type memory according to claim 1 and wherein said data strobe masking gating signal modifier is also operative to expand said expected data receipt duration indicating signal by less than a clock cycle prior to applying said variable time delay thereto.

3. Circuitry for reading from a double data rate type memory according to claim 1 and wherein said data strobe masking gating signal modifier is also operative to expand said expected data receipt duration indicating signal by one-half clock cycle prior to applying said variable time delay thereto.

4. Circuitry for reading from a double data rate type memory according to claim 1 and wherein said data strobe masking data signal modifier is configured to be operative to center said expected data receipt duration indicating signal about the midpoint of said duration of said data transmission using the following functionality:

a. applying to said expected data receipt duration indicating signal a first delay;

b. writing to said double data rate type memory at least a first burst of data;

c. reading from said double data rate type memory said at least a first burst of data;

d. comparing said at least a first burst of data obtained by said reading with said at least first burst of data written to said double data rate type memory during said writing in order to determine whether write/read data integrity exists for said first delay;

e. setting an initial data integrity delay to said first delay if write/read data integrity exists for said first delay;

f. repeating steps b., c. and d. for increasing delays until write/read data integrity is found to exist for an initial data integrity delay, if write/read data integrity does not exist for said first delay;

g. repeating steps b., c. and d. for further increasing delays until write/read data integrity is found to not to exist for a terminal data integrity delay; and

h. selecting an intermediate delay which is a function of said initial data integrity delay and said terminal data integrity delay and applying said intermediate delay as said variable time delay.

5. Circuitry for reading from a double data rate type memory according to claim 4 and wherein said functionality also comprises repeating steps a.-h. over time to compensate for variations in temperature and voltage.

6. Circuitry for reading from a double data rate type memory according to claim 1 and wherein said data strobe masking gating signal modifier is configured to be operative to center said expected data receipt duration indicating signal about the midpoint of said duration of said data transmission using the following functionality:

a. applying to said expected data receipt duration indicating signal a first delay;

b. writing to said double data rate type memory at least a first burst of data;

c. reading from said double data rate type memory said at least a first burst of data;

d. comparing said at least a first burst of data obtained by said reading with said at least first burst of data written to said double data rate type memory during said writing in order to determine whether write/read data integrity exists for said first delay;

e. setting an initial data integrity delay to said first delay if write/read data integrity exists for said first delay;

f. repeating steps c. and d. for increasing delays until write/read data integrity is found to exist for an initial data integrity delay, if write/read data integrity does not exist for said first delay;

g. repeating steps c. and d. for further increasing delays until write/read data integrity is found to not to exist for a terminal data integrity delay; and

h. selecting an intermediate delay which is a function of said initial data integrity delay and said terminal data integrity delay and applying said intermediate delay as said variable time delay.

7. Circuitry for reading from a double data rate type memory according to claim 1 and wherein said data strobe masking gating signal modifier is configured to be operative to center said expected data receipt duration indicating signal about the midpoint of said duration of said data transmission using the following functionality:

a. applying to said expected data receipt duration indicating signal a first delay;

b. writing to said double data rate type memory at least a first burst of data;

c. reading from said double data rate type memory said at least a first burst of data;

d. comparing said at least a first burst of data obtained by said reading with said at least first burst of data written to said double data rate type memory during said writing in order to determine whether write/read data integrity exists for said first delay;

e. setting an initial data integrity delay to said first delay if write/read data integrity exists for said first delay;

f. repeating steps c. and d. for increasing delays until write/read data integrity is found to exist for an initial data integrity delay, if write/read data integrity does not exist for said first delay;

f′. writing to said double data rate type memory at least a first burst of data;

g. repeating steps c. and d. for further increasing delays until write/read data integrity is found to not to exist for a terminal data integrity delay; and

h. selecting an intermediate delay which is a function of said initial data integrity delay and said terminal data integrity delay and applying said intermediate delay as said variable time delay.

8. Circuitry for reading from a double data rate type memory according to claim 1 and wherein said data strobe masking gating signal modifier is configured to be operative to center said expected data receipt duration indicating signal about the midpoint of said duration of said data transmission using the following functionality:

a. applying to said expected data receipt duration indicating signal a first delay;

b. writing to said double data rate type memory at least a first burst of data;

c. reading from said double data rate type memory said at least a first burst of data;

d. comparing said at least a first burst of data obtained by said reading with said at least first burst of data written to said double data rate type memory during said writing in order to determine whether write/read data integrity exists for said first delay;

e. setting an initial data integrity delay to said first delay if write/read data integrity exists for said first delay;

f. repeating steps b., c. and d. for increasing delays until write/read data integrity is found to exist for an initial data integrity delay, if write/read data integrity does not exist for said first delay; and

g. selecting an intermediate delay which is a function of said initial data integrity delay and applying said intermediate delay as said variable time delay.

9. Circuitry for reading from a double data rate type memory according to claim 1 and wherein said data strobe masking gating signal modifier is configured to be operative to center said expected data receipt duration indicating signal about the midpoint of said duration of said data transmission using the following functionality:

a. applying to said expected data receipt duration indicating signal a first delay;

b. writing to said double data rate type memory at least a first burst of data;

c. reading from said double data rate type memory said at least a first burst of data;

d. comparing said at least a first burst of data obtained by said reading with said at least first burst of data written to said double data rate type memory during said writing in order to determine whether write/read data integrity exists for said first delay;

e. setting an initial data integrity delay to said first delay if write/read data integrity exists for said first delay;

f. repeating steps c. and d. for increasing delays until write/read data integrity is found to exist for an initial data integrity delay, if write/read data integrity does not exist for said first delay; and

g. selecting an intermediate delay which is a function of said initial data integrity delay and applying said intermediate delay as said variable time delay.

10. Circuitry for reading from a double data rate type memory according to claim 1 and wherein said gate is an AND gate.

11. Circuitry for reading from a double data rate type memory according to claim 1 and also comprising drift detection circuitry operative to provide an indication of a timing relationship between a rising edge of said data strobe masking gating signal and a last falling edge of said data strobe signal to said control logic.

12. Circuitry for reading from a double data rate type memory according to claim 11 and wherein said indication comprises an indication of which one of three possible states of drift is present.

13. Circuitry for reading from a double data rate type memory according to claim 11 and wherein said data detection circuitry comprises:

a first latch supplying a first latch output;

a second latch supplying a second latch output;

a first delay line providing a first delay; and

a second delay line providing a second delay;

and said circuitry includes the following functionality:

receiving an input from said second bi-directional I/O interface;

providing a first latch input to said first latch, said first latch input to said first latch comprising said second delay of said data strobe signal;

providing a second latch input to said first latch, said second latch input to said first latch comprising said first delay of said data strobe masking gating signal;

providing a first latch input to said second latch, said first latch input to said second latch comprising said data strobe signal; and

providing a second latch input to said second latch, said second latch input to said second latch comprising said first delay of said data strobe masking gating signal,

wherein said indication is a function of said first latch output and said second latch output.

14. Circuitry for reading from a double data rate type memory according to claim 13 and wherein said input from said second bi-directional I/O interface comprises a delayed input.

15. Circuitry for reading from a double data rate type memory according to claim 13 and wherein said first delay comprises a 45 degree delay and said second delay comprises a 90 degree delay.

16. Circuitry for reading from a double data rate type memory according to claim 11 and wherein said control logic is operative to provide said extent of delay indicating signal based on said indication.