Integrated circuit communication self-testing
View Patent ↗An integrated circuit 2 includes a plurality of serial data transmitters 18 and a plurality of serial data receivers 20 . On-chip test signal paths 22 with associated on-chip test circuits 24, 26, 28 are provided so as to permit on-chip serial data communication to be performed with test characteristics imposed by the on-chip test circuits 24, 26, 28 thereby providing on-chip stress testing of the data transmitter 18 and the serial data receiver 20.
1. An integrated circuit comprising:
at least one serial data transmitter;
at least one serial data receiver coupled to said at least one serial data transmitter to provide data communication therewith; and
at least one on-chip test circuit disposed in a test signal path between said at least one serial data transmitter and said at least one serial data receiver to generate at least one test characteristic in a serial data signal sent therebetween so as to stress test said data communication.
2. An integrated circuit as claimed in claim 1 , wherein said at least one on-chip test circuit includes an impedance generating circuit providing a programmable impedance characteristic in said test signal path.
3. An integrated circuit as claimed in claim 2 , wherein said impedance generating circuit includes a programmable resistance circuit providing a programmable serial resistance in said test signal path.
4. An integrated circuit as claimed in claim 2 , wherein said impedance generating circuit includes a programmable capacitance circuit providing a programmable capacitance between said test signal path and a signal ground.
5. An integrated circuit as claimed in claim 2 , wherein said impedance generating circuit is disposed between said test signal path and said at least one serial data receiver.
6. An integrated circuit as claimed in claim 1 , comprising a plurality of serial data communication circuits, each serial data communication circuit comprising a serial data transmitter and a serial data receiver, and at least one test signal path providing data communication from a serial data transmitter of a first serial data communication circuit and a serial data receiver of a second serial data communication circuit.
7. An integrated circuit as claimed in claim 6 , wherein each serial data communication circuit comprises an on-chip test circuit.
8. An integrated circuit as claimed in claim 6 , comprising a plurality of test signal paths between said plurality serial data communication circuits.
9. An integrated circuit as claimed in claim 7 , wherein each serial data communication circuit comprises an on-chip test circuit and each on-chip test circuit comprises a programmable connection circuit providing a programmable connection to one or more of said plurality of test signal paths.
10. An integrated circuit as claimed in claim 8 , comprising a crosstalk capacitance circuit providing a programmable capacitive coupling between at least two of said plurality of test signal paths so as to generate crosstalk interference therebetween.
11. An integrated circuit comprising:
at least one serial data transmitting means for transmitting serial data;
at least one serial data receiving means for receiving serial data, said at least one serial data receiving being coupled to said at least one serial data transmitting means to provide data communication therewith; and
at least one on-chip test means disposed in a test signal path between said at least one serial data transmitting means and said at least one serial data receiving means for generating at least one test characteristic in a serial data signal sent therebetween so as to stress test said data communication.
12. A method of testing an integrated circuit, said method comprising the steps of:
transmitting serial data using at least one serial data transmitter;
receiving serial data using at least one serial data receiver coupled to said at least one serial data transmitting means to provide data communication therewith; and
generating at least one test characteristic in a serial data signal so as to stress test said data communication using at least one on-chip test means disposed in a test signal path between said at least one serial data transmitter and said at least one serial data receiver.