Digital extraction and correction of the linearity of a residue amplifier in a pipeline ADC

1. A pipeline analog-to-digital converter, comprising:

a stage, the stage including a residue amplifier that amplifies a residual voltage generated by the stage to obtain an amplified residual voltage;

a backend digitizer that digitizes the amplified residual voltage to generate a digitized residual; and

a digital correction circuit that determines an operating zone from a plurality of zones of a transfer function that is associated with the digitized residual by comparing the digitized residual with operating parameters of the operating zone and corrects the digitized residual according to which operating zone the digitized residual is found.

2. The pipeline analog-to-digital converter of claim 1 , wherein the stage includes

an analog-to-digital converter that digitizes an analog input voltage V IN to generate a digital value D flash ,

a digital-to-analog converter that converts D flash to an analog voltage V flash ,

a first summer that subtracts the analog voltage V flash from the input voltage V IN to generate a first residual voltage,

a one-bit digital-to-analog converter that generates an analog voltage from a pseudo-random digital sequence,

a second summer that receives the first residual voltage and adds the analog voltage from the pseudo-random digital sequence to generate the second residual voltage, and

wherein the residue amplifier amplifies the second residual voltage.

3. The pipeline analog-to-digital converter of claim 2 , wherein the digital correction includes

a gain extraction that generates a value K 0 given a corrected digital residual,

zoned integrators that receive the value K 0 according to the operating zone;

a gain correction that receives a gain correction parameter from a first integrator in the zoned integrators and provides a first correction to the digital residual, and

a linearity correction that receives a linearity correction parameter from a second integrator in the zoned integrators and provides a second correction to the digital residual.

4. The pipelined analog-to-digital converter of claim 3 , further including a second linearity correction that receives a second linearity correction parameter from a third integrator in the zoned integrators and provides a third correction to the digital residual.

5. The pipelined analog-to-digital converter of claim 3 , wherein the gain extraction includes

multiplying the digital residual with the pseudo random digital sequence to generate the value K 0 .

6. The pipelined analog-to-digital converter of claim 3 , wherein the zoned integrators includes a switch coupled to a zone extraction circuit, the zone extraction circuit determining the operating zone based on the digitized residual, the switch providing the value K 0 to one or more integrators based on the switch.

7. The pipelined analog-to-digital converter of claim 3 , wherein the gain correction includes a multiplier that multiplies the digitized residual by the gain correction factor γ c0 that is added to the digitized residual in the first correction.

8. The pipelined analog-to-digital converter of claim 3 , wherein the linearity correction includes a first multiplier that calculates a cube of the digitized residual and a second multiplier that multiplies the cube of the digitized residual by the linearity correction parameter, the result being added to the digitized residual as the second correction.

9. A method of correction in a pipeline ADC, comprising

determining a gain parameter based on a backend digitized value;

determining an operating zone from a plurality of zones of a transfer function that is associated with the backend digitized value by comparing the backend digitized value with operating parameters of the operating zone to determine the operating zone;

integrating the gain parameter in one of a plurality integrators associated with the operating zone;

providing a correction of the backend digitized value associated with operation within each of the plurality of zones using parameters from the integrator associated with each of the plurality of zones.

10. The method of claim 9 , wherein determining the gain parameter includes multiplying a corrected backend digitized value by a pseudo random digitize sequence that was added during a stage of the pipeline ADC.

11. The method of claim 9 , wherein integrating the gain parameter includes determining which of the plurality of integrators is associated with the operating zone and providing the gain parameter to the associated integrator.

12. The method of claim 11 , wherein providing a correction of the backend digitized value includes

providing a gain correction; and

providing a linearity correction.

13. The method of claim 12 , wherein providing a gain correction includes

receiving a gain correction factor from a first integrator of the plurality of integrators that is associated with a linear zone;

multiplying the gain correction factor by the backend digitized value to provide a gain correction; and

adding the gain correction to the backend digitized value to provide a first correction.

14. The method of claim 12 , wherein providing a linearity correction includes

receiving a linearity correction factor from a second integrator of the plurality of integrators that is associated with a nonlinear zone;

calculating a cube of a value related to the backend digitized value;

multiplying the cube by the linearity correction factor to generate the linearity correction; and

adding the linearity correction to the value to provide a second correction.

15. The method of claim 14 , wherein the value is the first correction.