Fractional-N dividers having divider modulation circuits therein with segmented accumulators

1. A fractional-N divider circuit, comprising:

a multi-modulus divider configured to perform at least /N and /N+1 frequency division of a first reference signal received at a first input thereof in response to an overflow signal received at a second input thereof, where N is an integer greater than one;

a phase correction circuit configured to generate a second reference signal in response to a divider output signal generated by said multi-modulus divider, said second reference signal having a duty cycle that is more nearly uniform relative to the divider output signal;

a divider modulation circuit configured to generate the overflow signal in response to a code that specifies a plurality of division moduli to be used by said multi-modulus divider during the at least /N and /N+1 frequency division of the first reference signal, said divider modulation circuit comprising a segmented accumulator configured to generate a plurality of segments of a count value having at least one period of latency therebetween; and

a phase error calculator configured to provide at least one segment of the count value to said phase correction circuit.

2. The divider circuit of claim 1 , wherein the code is a digital code that specifies a repeating sequence of division moduli to be used by said multi-modulus divider during the at least /N and /N+1 frequency division of the first reference signal.

3. The divider circuit of claim 1 , wherein said phase correction circuit comprises a pulse-width locked loop.

4. The divider circuit of claim 3 , wherein said pulse-width locked loop comprises a delay line having a plurality of voltage-controlled delay cells therein.

5. The divider circuit of claim 3 , wherein said phase correction circuit comprises a latch having a synchronization terminal responsive to the divider output signal; and wherein the second reference signal is fed back to a data input terminal of the latch.

6. The divider circuit of claim 1 , wherein said phase correction circuit is responsive to a digital quantization error generated by said divider modulation circuit and said phase error calculator.

7. A fractional-N divider circuit, comprising:

a multi-modulus divider configured to perform at least /N and /N+1 frequency division of a first reference signal received at a first input thereof in response to an overflow signal received at a second input thereof, where N is an integer greater than one;

a phase correction circuit configured to generate a second reference signal in response to a divider output signal generated by said multi-modulus divider, said second reference signal having a duty cycle that is more nearly uniform relative to the divider output signal; and

a divider modulation circuit configured to generate the overflow signal in response to a digital code that specifies a plurality of division moduli to be used by said multi-modulus divider during the at least /N and /N+1 frequency division of the first reference signal, said divider modulation circuit comprising a segmented accumulator configured to generate a plurality of segments of a count value having at least one period of latency therebetween, said segmented accumulator comprising a first accumulator segment responsive to a plurality of least significant bits of the digital code and last accumulator segment responsive to a plurality of most significant bits of the digital code.

8. The divider circuit of claim 7 , wherein each of the first and last accumulator segments is synchronized to an accumulator clock signal and generates a respective segment overflow signal.

9. The divider circuit of claim 7 , wherein each of the first and last accumulator segments is synchronized to the divider output signal.

10. The divider circuit of claim 9 , wherein said phase correction circuit comprises a pulse-width locked loop.

11. The divider circuit of claim 7 , further comprising a phase error calculator configured to provide at least one segment of the count value to said phase correction circuit.

12. A fractional-N divider circuit, comprising:

a multi-modulus divider configured to perform at least /N and /N+1 frequency division of a first reference signal received at a first input thereof in response to an overflow signal received at a second input thereof, where N is an integer greater than one;

a phase correction circuit configured to generate a second reference signal in response to a divider output signal generated by said multi-modulus divider, said phase correction circuit comprising:

a duty cycle adjustment circuit responsive to the divider output signal and a feedback signal derived from the second reference signal; and

a phase interpolator responsive to at least one signal generated by said duty cycle adjustment circuit;

a divider modulation circuit configured to generate the overflow signal in response to a code that specifies a plurality of division moduli to be used by said multi-modulus divider during the at least /N and /N+1 frequency division of the first reference signal; and

a phase error calculator configured to provide at least one segment of a count value generated by said divider modulation circuit to said phase correction circuit.

13. The divider circuit of claim 12 , wherein the at least one signal has an approximately uniform duty cycle.

14. The divider circuit of claim 12 , wherein the second reference signal has a duty cycle that is more nearly uniform relative to the divider output signal.

15. The divider circuit of claim 12 , wherein said divider modulation circuit comprises a segmented accumulator configured to generate a plurality of segments of the count value having at least one period of latency therebetween.

16. A fractional-N divider circuit, comprising:

a multi-modulus divider configured to perform at least /N and /N+1 frequency division of a first reference signal received at a first input thereof in response to an overflow signal received at a second input thereof, where N is an integer greater than one;

a phase correction circuit configured to generate a second reference signal in response to a divider output signal generated by said multi-modulus divider, said phase correction circuit comprising:

a duty cycle adjustment circuit responsive to the divider output signal and a feedback signal derived from the second reference signal, said duty cycle adjustment circuit comprising a pair of latches having data terminals responsive to the feedback signal and clock terminals responsive to true and complementary versions of the divider output signal; and

a phase interpolator responsive to at least one signal generated by said duty cycle adjustment circuit; and

a divider modulation circuit configured to generate the overflow signal in response to a code that specifies a plurality of division moduli to be used by said multi-modulus divider during the at least /N and /N+1 frequency division of the first reference signal.

17. The divider circuit of claim 16 , wherein the phase interpolator is responsive to a pair of signals derived from outputs of the pair of latches.

18. A fractional-N divider circuit, comprising:

a multi-modulus divider configured to perform at least /N and /N+1 frequency division of a first reference signal received at a first input thereof in response to an overflow signal received at a second input thereof, where N is an integer greater than one;

a phase correction circuit configured to generate a second reference signal in response to a divider output signal generated by said multi-modulus divider, said phase correction circuit comprising:

a duty cycle adjustment circuit responsive to the divider output signal and a feedback signal derived from the second reference signal; and

a phase interpolator responsive to at least one signal generated by said duty cycle adjustment circuit; and

a divider modulation circuit configured to generate the overflow signal in response to a digital code that specifies a repeating sequence of division moduli to be used by said multi-modulus divider during the at least /N and /N+1 frequency division of the first reference signal, said divider modulation circuit comprising a segmented accumulator configured to generate a plurality of segments of a count value having at least one period of latency therebetween, said segmented accumulator comprising a first accumulator segment responsive to a plurality of least significant bits of the digital code and last accumulator segment responsive to a plurality of most significant bits of the digital code.

19. The divider circuit of claim 18 , wherein each of the first and last accumulator segments is synchronized to an accumulator clock signal and generates a respective segment overflow signal.

20. The divider circuit of claim 18 , wherein each of the first and last accumulator segments is synchronized to a synchronizing signal derived from the second reference signal.

21. The divider circuit of claim 20 , wherein the synchronizing signal has a frequency greater than a frequency of the second reference signal.