IP Library Granted Patent US 8,638,174
Granted Patent B2
US 8,638,174 · App. 13/116,967 · Granted Jan 28, 2014

Digital signal generator

Inventors: Nenad Pavlovic (Eindhoven, NL); Johannes Hubertus Antonius Brekelmans (Nederweert, NL); Jan van Sinderen (Liempde, NL)
Assignee: Integrated Device Technology inc.
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Quick Facts
Patent No.
US 8,638,174
App. No.
13/116,967
Granted
Jan 28, 2014
Kind
B2
Abstract

The invention relates to a digital signal generator for providing one or more phases of a local oscillator signal for use in digital to analogue converters and harmonic rejection mixers. Embodiments disclosed include a local oscillator signal generator ( 200 ) for a mixer of a radiofrequency receiver, the signal generator ( 200 ) comprising a bit sequence generator ( 201 ) having a plurality of parallel output lines ( 203 ), a digital signal generator ( 202 ) having a serial output line ( 204 ) and a plurality of input lines connected to respective output lines ( 203 ) of the bit sequence generator ( 201 ) and a clock signal input line ( 205 ), wherein the digital signal generator ( 202 ) is configured to provide an output bit sequence on the serial output line ( 204 ) at a rate given by a clock signal provided on the clock signal input line ( 205 ) and a sequence given by a sequence of bits from the bit sequence generator ( 201 ) on the plurality of input lines ( 203 ).

Claims (24)

1. A local oscillator signal generator for a mixer of a radiofrequency receiver, the signal generator comprising:

a bit sequence generator having a plurality of parallel output lines;

a digital signal generator having a serial output line, a plurality of input lines connected to respective output lines of the bit sequence generator, and a plurality of parallel to serial multiplexer modules, each multiplexer module configured to provide a serial output from a pair of parallel inputs; and

a clock signal input line connected to the digital signal generator,

wherein the digital signal generator is configured to provide an output bit sequence on the serial output line to the mixer at a rate given by a single-phase clock signal provided to the digital signal generator on the clock signal input line and a sequence given by a sequence of bits from the bit sequence generator on the plurality of input lines.

2. The local oscillator signal generator of claim 1 wherein the bit sequence generator comprises 2 n parallel output lines where n is a positive integer, and wherein the multiplexer modules are arranged in stages from a first stage comprising one multiplexer module to an n th stage comprising 2 n-1 multiplexer modules, the second to n th having twice the number of modules of a preceding stage and having serial outputs connected to parallel inputs of modules of the immediately preceding stage.

3. The local oscillator signal generator of claim 2 comprising n−1 clock signal dividers configured to provide an output clock signal at half the rate of an input clock signal and connected between clock signal inputs of multiplexer modules of adjacent stages,

wherein the clock signal input line is connected to a first one of the clock signal dividers and to the clock signal input of the multiplexer module of the first stage such that the multiplexer module of the first stage provides the serial digital signal output at the rate of a clock signal applied to the clock signal input line.

4. The local oscillator signal generator of claim 3 wherein an output of the n−1 th clock signal divider is connected to a clock signal input of the bit sequence generator.

5. The local oscillator signal generator of claim 4 wherein the bit sequence generator is configured to provide successive bit sequences to the parallel inputs of multiplexer modules of the n th stage in response to successive pulses of a clock signal applied to the clock signal input from the n−1 th clock signal divider.

6. The local oscillator signal generator of claim 4 or claim 5 wherein the output of the n−1 th clock signal divider is connected to the clock signal input of the bit sequence generator via an inverted output.

7. The local oscillator signal generator claim 2 , wherein n is greater than or equal to 2.

8. The local oscillator signal generator of claim 1 , comprising a sequence of shift registers connected in series to the serial output of the digital signal generator.

9. A local oscillator signal generator for a mixer of a radiofrequency receiver, the signal generator comprising:

a plurality of memory modules, each having a plurality of parallel output lines;

a plurality of digital signal generator modules each having a serial output line and a plurality of input lines;

a bit shifter module coupled to the pluralities of parallel output lines of the plurality of memory modules and to the pluralities of input lines of the plurality of digital signal generator modules; and

a clock signal input line,

wherein each digital signal generator module is configured to provide an output bit sequence to the mixer on the serial output line at a rate given by a single-phase clock signal provided on the clock signal input line and a sequence given by a sequence of bits from a corresponding memory on the plurality of input lines.

10. A method of operating a local oscillator signal generator, the method comprising:

generating a sequence of bits at a bit sequence generator having a plurality of parallel output lines;

providing the sequence to a digital signal generator at a plurality of parallel input lines, the parallel input lines coupled to a plurality of parallel to serial multiplexer modules, each multiplexer module configured to provide a serial output from a pair of parallel inputs;

providing a single-phase clock signal to the digital signal generator on a clock signal input line; and

providing an output bit sequence on a serial output line of the digital signal generator to a mixer at a rate given by the single-phase clock signal provided on the clock signal line and corresponding to the sequence of bits from the bit sequence generator.

Assignments (14)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 29, 2019
From: JPMORGAN CHASE BANK, N.A.
To: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; CHIPX, INCORPORATED; ENDWAVE CORPORATION; MAGNUM SEMICONDUCTOR, INC.
Reel/Frame 048746/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
SECURITY AGREEMENT Recorded Apr 5, 2017
From: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; MAGNUM SEMICONDUCTOR, INC.; ENDWAVE CORPORATION; CHIPX, INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 042166/0431 →
PATENT RELEASE Recorded Aug 17, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 039707/0471 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 30, 2012
From: NXP B.V.
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 029213/0890 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 26, 2011
From: PAVLOVIC, NENAD; BREKELMANS, JOHANNES HUBERTUS ANTONIUS; VAN SINDEREN, JAN
To: NXP B.V.
Reel/Frame 026350/0419 →
Priority Claims (1)
EP 10250980 · May 26, 2010 · regional
Continuity (1)
Related Publication 20110291732A1 · Dec 1, 2011