Stress-relieved shallow trench isolation (STI) structure and method for forming the same
View Patent ↗A shallow trench isolation (STI) structure in a semiconductor substrate and a method for forming the same are provided. A trench is formed in a semiconductor substrate. A first dielectric layer is formed on sidewalls of the trench. The first dielectric layer is formed thicker at a top portion of the sidewalls than a bottom portion of the sidewalls and leaving an entrance of the trench open to expose the trench. A second dielectric layer is conformally formed on the first dielectric layer to close the entrance, thus forming a void buried within the trench. Thus, the stress between the trench dielectric layer and the surrounding silicon substrate during thermal cycling can be substantially reduced.
1. A method for forming a shallow trench isolation (STI) structure in a semiconductor substrate, the method comprising:
forming a trench in a semiconductor substrate;
forming a first dielectric layer on sidewalls of the trench, the first dielectric layer being formed thicker at a top portion of the sidewalls than a bottom portion of the sidewalls and leaving an entrance of the trench open to expose the trench; and
conformally forming a second dielectric layer on the first dielectric layer to close the entrance and form a void buried within the trench.
2. The method of claim 1 , further comprising planarizing the substrate including the second dielectric layer to form an STI structure.
3. The method of claim 1 , wherein forming the first dielectric layer comprises performing a plasma enhanced chemical vapor deposition (PE-CVD) process.
4. The method of claim 3 , further comprising annealing after forming the first dielectric layer.
5. The method of claim 3 , wherein the first dielectric layer is formed of plasma-enhanced tetraethoxysilane-based (PE-TEOS) oxide or plama-enhanced silane-based (PE-SiH 4 ) CVD oxide.
6. The method of claim 1 , wherein forming the first dielectric layer comprises performing a high-density plasma chemical vapor deposition (HDP-CVD) process.
7. The method of claim 1 , wherein the second dielectric layer is formed of 03-TEOS oxide or HDP-CVD oxide.
8. The method of claim 1 , wherein the first dielectric layer is formed by HDP-CVD with no power or a power of about 1500 to 2000 W and the second dielectric layer is formed by HDP-CVD with a power of about 3000 to 4000 W.
9. The method of claim 1 , wherein the first dielectric layer is formed to a thickness of about 300 to 700 angstroms.
10. The method of claim 1 , wherein the second dielectric layer is formed to a thickness of about 8000 angstroms.
11. The method of claim 1 , wherein the volume of the void is at least about 5 percent of the total volume of the insulating layer within the trench to absorb a thermo-mechanical stress during thermal cycling.
12. The method of claim 11 , wherein the volume of the void is about 10 percent.
13. The method of claim 1 , wherein forming the isolation trenches further comprises:
forming a pad oxide layer on the semiconductor substrate;
forming a silicon nitride layer on the pad oxide layer;
patterning the silicon nitride layer to define the trench; and
etching the semiconductor substrate using the patterned silicon nitride layer as a mask to form the trench in the semiconductor substrate.
14. A method for forming a shallow trench isolation (STI) structure in a semiconductor substrate, the method comprising:
forming a first opening depthwise in a semiconductor substrate;
forming a first dielectric layer on sidewalls of the first opening to form a second opening having a bottleneck structure so that a top portion of the second opening is substantially narrower than a bottom portion of the second opening, wherein an entrance of the second opening is left open to expose the trench; and
conformally forming a second dielectric layer on the first dielectric layer to close the entrance of the second opening and form a void buried within the trench.