IP Library › Granted Patent US 7,133,951

Granted Patent B1

US 7,133,951 · App. 09/515,358 · Granted Nov 7, 2006

Alternate set of registers to service critical interrupts and operating system traps

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Quick Facts

Patent No.: US 7,133,951
App. No.: 09/515,358
Granted: Nov 7, 2006
Kind: B1

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Abstract

A processor includes a set of general purpose registers that are used when executing generic tasks and a set of exception registers that is dedicated for servicing specific exceptions. When a task is interrupted with an asserted “fast” exception, the processor automatically diverts the exception to the dedicated exception registers using a dedicated vector. The dedicated vector and exception registers may be reserved for high priority, i.e., critical, exceptions. Because the exception registers are automatically activated for fast exceptions, there is no need to determine the priority of the exception. Further, high priority interrupts and high priority operating system calls (traps) may have different dedicated vectors and the set of exception registers may have a portion allocated for servicing interrupts and another portion allocated for servicing operating system calls. With the use of a dedicated vector or dedicated vectors, there is no need for software to decode the fast exception. Advantageously, during the servicing of the exception, the values of the exception registers may be modified, without disrupting the state of the interrupted task. Thus, because a set of dedicated exception registers are swapped in for the general purpose registers to service an exception, there is no need for explicit state management prior to or after servicing the exception.

Claims (90)

1. A processor comprising:

a set of general purpose registers; and

a set of dedicated exception registers that are switched for a subset of said set of general purpose registers during servicing of an exception, wherein said set of exception registers is substantially dedicated for servicing exceptions;

wherein a portion of said set of exception registers is for servicing interrupts and another portion of said set of exception registers is for servicing operating system calls;

wherein at least one general purpose register that is not switched to service exceptions is configured to allow access by said processor during said servicing of an exception.

2. The processor of claim 1 , wherein said set of exception registers is for servicing exceptions having a high priority not for those exceptions having a low priority.

3. The processor of claim 1 , wherein said processor provides a dedicated vector to said set of exception registers for said exception.

4. The processor of claim 1 , wherein there are at least eight exception registers.

5. The processor of claim 1 , wherein said processor provides a first dedicated vector to software which uses said portion of said set of exception registers for interrupts and a second dedicated vector to software which uses said another portion of said set of exception registers for servicing operating system calls.

6. The processor of claim 1 , further comprising:

a select logic circuit having a first input terminal that receives an exception register active bit and a second input terminal that receives a register address bit, said select logic circuit provides an output signal on an output terminal used to select between said set of general purpose registers and said exception registers.

7. A method of interrupting the execution of a task and servicing an exception in a processor, said method comprising:

swapping a set of general purpose registers for at least one set of exception registers if an exception asserted at said processor is a high priority exception;

servicing said exception using said at least one set of exception registers if said exception is a high priority exception;

preserving information from the set of general purpose registers in a memory if said exception is a low priority exception; and

swapping out said exception registers for said set of general purpose registers and resuming execution of said task if said exception is a high priority exception;

wherein servicing said exception using said at least one set of exception registers comprises modifying the values of the registers in said set of exception registers without disrupting the state of the interrupted task; and

wherein during servicing of an exception, a subset of said set of general purpose registers are not replaced with an alternate set and the subset of said set of general purpose registers that are not replaced with an alternate set allow data sharing between exception processing and normal execution.

8. A method of interrupting the execution of a task and servicing an exception in a processor, said method comprising:

swapping a set of general purpose registers for at least one set of exception registers if an exception asserted at said processor is a high priority exception;

servicing said exception using said at least one set of exception registers if said exception is a high priority exception;

preserving information from the set of general purpose registers in a memory if said exception is a low priority exception; and

swapping out said exception registers for said set of general purpose registers and resuming execution of said task if said exception is a high priority exception;

wherein a portion of said set of exception registers is for servicing interrupts and another portion of said set of exception registers is for servicing operating system calls; and

9. The method of claim 8 , wherein said at least one set of exception registers is a dedicated set of exception registers.

10. The method of claim 8 wherein said servicing comprises providing a first vector and activating said at least one set of exception registers for said high priority exception, and wherein said providing comprises providing a second vector and not activating said set of exception registers for lower priority exceptions.

11. The method of claim 10 , wherein said first vector is a dedicated vector and said providing said first vector automatically separates said high priority exception from said lower priority exceptions.

12. The method of claim 8 , wherein servicing said exception using said at least one set of exception registers comprises modifying the values of the registers in said set of exception registers without disrupting the state of the interrupted task.

13. The method of claim 8 , wherein said exception is a high priority exception and is either an interrupt or an operating system call, said method further comprising:

providing a first vector and activating at least a portion of said exception registers for said high priority exception when said exception is an interrupt; providing a second vector and activating at least another portion of said exception registers for said high priority exception when said exception is an operating system call; and

providing a third vector and not activating said set of exception registers for lower priority exceptions.

14. A method of interrupting the execution of a task and servicing an exception in a processor, said method comprising:

swapping a set of general purpose registers for at least one set of exception registers if an exception asserted at said processor is a high priority exception;

servicing said exception using said at least one set of exception registers if said exception is a high priority exception;

preserving information from the set of general purpose registers in a memory if said exception is a low priority exception; and

swapping out said exception registers for said set of general purpose registers and resuming execution of said task if said exception is a high priority exception;

wherein said exception is a high priority exception and is either an interrupt or an operating system call, said method further comprising:

providing a first vector and activating at least a portion of said exception registers for said high priority exception when said exception is an interrupt;

providing a second vector and activating at least another portion of said exception registers for said high priority exception when said exception is an operating system call; and

providing a third vector and not activating said set of exception registers for lower priority exceptions;

15. The method of claim 14 , wherein said first vector and said second vector are dedicated vectors and said providing said first vector and providing said second vector automatically separates said high priority exception from said lower priority exceptions.

16. An apparatus for executing tasks and servicing exceptions, said apparatus comprising:

means for interrupting a task when an exception is asserted;

means for servicing said exception without disrupting the state of the interrupted task, including means for activating at least one set of dedicated exception registers; and

means for resuming execution of said interrupted task, including means for deactivating said dedicated exception registers and activating general purpose registers to resume execution of said task;

wherein a portion of said set of exception registers is for servicing interrupts and another portion of said set of exception registers is for servicing operating system calls; and

17. The apparatus of claim 16 , wherein said means for activating comprises a first select logic circuit coupled to said set of general purpose registers and a second select logic circuit coupled to said at least one set of exception registers, said second select logic circuit receives an execution register active bit enabling said at least one set of exception registers and said second select logic circuit receives an inverted execution register active bit disabling said set of general purpose registers.

18. A processor comprising:

a set of general purpose registers; and

a set of dedicated exception registers that are switched for a subset of said set of general purpose registers only when an exception having at least a predetermined priority level is detected by said processor and that are not switched when an exception having a priority less than the predetermined priority level is detected by said processor;

wherein a portion of said set of exception registers is for servicing interrupts and another portion of said set of exception registers is for servicing operating system calls;

wherein at least one general purpose register that is not switched to service exceptions is configured to allow modification of the register states by said processor during said servicing of an exception.

19. The processor of claim 18 further comprising another set of dedicated exception registers that are switched for at least a subset of said set of general purpose registers only when another exception having at least said predetermined priority level is detected by the processor while said set if dedicated exception registers are switched for at least the subset of said set of general purpose registers.

20. The processor of claim 18 further comprising a select logic circuit having a first input that receives an exception register active bit and a second input that receives a register address bit, said select logic circuit provides an output signal on an output used to select between said set of general purpose registers and said exception registers.

21. The processor of claim 18 wherein said set of dedicated exception registers is switched only when an exception, of a first type, having at least a predetermined priority level is detected by said processor and the processor further comprising another set of dedicated exception registers that are switched for at least a subset of said set of general purpose registers only when another exception, of a second type, having at least said predetermined priority level is detected by the processor.

22. A processor comprising:

a set of general purpose registers; and

wherein a portion of said set of exception registers is for servicing interrupts and another portion of said set of exception registers is for servicing operating system calls;

wherein at least one general purpose register that is not switched to service exceptions is configured to allow access by said processor during said servicing of an exception such that said processor can modify register states of said at least one general purpose register.

23. A processor comprising:

a set of general purpose registers; and

wherein a portion of said set of exception registers is for servicing interrupts and another portion of said set of exception registers is for servicing operating system calls;

wherein at least one general purpose register that is not switched to service exceptions is configured to be read and written directly by said processor during said servicing of an exception.

24. A processor comprising:

a set of general purpose registers; and

wherein a portion of said set of exception registers is for servicing interrupts and another portion of said set of exception registers is for servicing operating system calls; and

25. A processor comprising:

a set of general purpose registers; and

wherein a portion of said set of exception registers is for servicing exceptions and another portion of said set of exception registers is for servicing operating system state and information calls;

wherein at least one general purpose register that is not switched to service exceptions is configured to be read and written directly by said processor during said servicing of an exception.

26. The processor of claim 25 wherein the portion of said set of exception registers for servicing exceptions is adapted to servicing interrupts.

27. A processor comprising:

a set of general purpose registers; and

wherein a portion of said set of exception registers is for servicing exceptions and another portion of said set of exception registers is for servicing operating system state and information calls; and

28. The processor of claim 27 wherein the portion of said set of exception registers for servicing exceptions is adapted to servicing interrupts.

29. A processor comprising:

a set of general purpose registers; and

wherein a portion of said set of exception registers is for servicing interrupts and another portion of said set of exception registers is for servicing operating system calls; and

wherein at least one general purpose register that is not switched to service exceptions is configured to be read and written directly by said processor during said servicing of an exception.

Assignments (2)

RELEASE OF SECURITY INTEREST Recorded Mar 29, 2019

From: JPMORGAN CHASE BANK, N.A.

To: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; CHIPX, INCORPORATED; ENDWAVE CORPORATION; MAGNUM SEMICONDUCTOR, INC.

Reel/Frame 048746/0001 →

SECURITY AGREEMENT Recorded Apr 5, 2017

From: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; MAGNUM SEMICONDUCTOR, INC.; ENDWAVE CORPORATION; CHIPX, INCORPORATED

To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT

Reel/Frame 042166/0431 →