Apparatuses and methods for a level shifter with reduced shoot-through current

1. A level-shifting circuit, comprising:

an output circuit comprising:

a pull-up circuit coupled to a high-voltage source and configured for pulling up a voltage on an output signal in response to a high-side control signal; and

a pull-down circuit coupled in series between a low-voltage source and the pull-up circuit, wherein the pull-down circuit is configured for pulling down the voltage on the output signal in response to a low-side control signal;

a high-side inverting buffer operably coupled to the output circuit and configured to drive the high-side control signal responsive to an edge-controlled signal;

a low-side buffer configured to drive the low-side control signal responsive to an input signal; and

an edge-control buffer including a current minor operably coupled to the high-side inverting buffer, wherein the current mirror is configured to mirror a pull-up control current from one side of the current mirror into the edge-controlled signal, wherein the edge-controlled signal exhibits a slow rise time relative to a fall time of the edge-control signal.

2. The level-shifting circuit of claim 1 , wherein the edge-control buffer is further configured to generate the edge-controlled signal to rise slowly relative to a rise time of the input signal to the low-side buffer.

3. The level-shifting circuit of claim 1 , wherein the pull-up circuit comprises a PMOS transistor, and the pull-down circuit comprises an NMOS transistor, wherein:

a drain of the PMOS transistor is operably coupled to a drain of the NMOS transistor;

a source of the PMOS transistor is operably coupled to the high-voltage source;

a source of the NMOS transistor is operably coupled to the low-voltage source;

a gate of the PMOS transistor is operably coupled to the high-side inverting buffer to receive the high-side control signal; and

a gate of the NMOS transistor is operably coupled to the low-side buffer to receive the low-side control signal.

4. The level-shifting circuit of claim 3 , further comprising a Zener diode operably coupled between the high-voltage source and an input to the high-side inverting buffer, wherein the Zener diode is configured to limit a voltage to be no greater than a maximum Vgs voltage of the high-side inverting buffer.

5. The level-shifting circuit of claim 3 , wherein the edge-control buffer comprises a second NMOS transistor configured to control an input to the high-side inverting buffer, wherein a drain of the second NMOS transistor is operably coupled to the input of the high-side inverting buffer, a gate of the second NMOS transistor is operably coupled to an inverted input signal, and a source of the second NMOS transistor is operably coupled to a pull-down control current.

6. The level-shifting circuit of claim 5 , wherein the pull-down control current is greater than the pull-up control current.

7. The level-shifting circuit of claim 1 , wherein the low-side buffer comprises a turn-on delay operably coupled to an input of the pull-down circuit, wherein the turn-on delay is configured to delay the low-side control signal.

8. The level-shifting circuit of claim 5 , wherein the edge-control buffer further comprises a speed-up capacitor operably coupled in parallel with the pull-down control current, wherein the speed-up capacitor is configured to drive a large current relative to the pull-up control current at a transition of the second NMOS transistor.

9. The level-shifting circuit of claim 8 , wherein the edge-control buffer further comprises a discharge device operably coupled in parallel with the speed-up capacitor, wherein the discharge device is configured to discharge the speed-up capacitor in response to the input signal being asserted.

10. The level-shifting circuit of claim 1 , wherein the low-voltage source is at least one of ground and a negative voltage.

11. The level-shifting circuit of claim 1 , wherein the high-side inverting buffer comprises a multi-stage inverter configured to drive the high-side control signal.

12. The level-shifting circuit of claim 1 , wherein the low-side buffer comprises an inverter configured to drive the low-side control signal.

13. The level-shifting circuit of claim 12 , further comprising a low-side edge-control buffer operably coupled between the input signal and the low-side buffer and configured to generate a low-side edge-controlled signal with a fast rise time relative to a fall time of the low-side edge-controlled signal.

14. The level-shifting circuit of claim 1 , wherein the high-side control signal and the low-side control signal have non-overlap timing of the rise times of the high-side control signal and the low-side control signal and of the fall times of the high-side control signal and the low-side control signal when alternatingly pulling up and pulling down the voltage on the output signal.

15. The level-shifting circuit of claim 1 , wherein:

the high-side inverting buffer and the low-side inverting buffer each comprise at least one low-voltage device, wherein the at least one low-voltage device of the high-side inverting buffer is configured to operate in a high-side low-voltage swing between the high-voltage source and a differential voltage less than the high-voltage source, and the at least one low-voltage device of the low-side buffer is configured to operate in a low-side low-voltage swing between the low-voltage source and a differential voltage above the low-voltage source; and

the output circuit comprises at least one high-voltage device configured for operation at voltages above a safe Vgs voltage of the low-voltage devices.

16. A method for shifting an input voltage level to a different output voltage level, the method comprising:

generating an edge-controlled signal including mirroring a pull-up control current onto the edge-controlled signal, the edge-controlled signal exhibiting a slow rise time relative to a fall time of the edge-controlled signal;

generating a high-side control signal by inverting the edge-controlled signal, the high-side control signal controlling a pull-up device of an output circuit;

generating a low-side control signal controlling a pull-down device of the output circuit responsive to an inverted input signal; and

toggling an output voltage level of an output voltage signal between a high-voltage level and a low-voltage level responsive to transitions of the high-side control signal and the low-side control signal.

17. The method of claim 16 , wherein generating the high-side control signal and generating the low-side control signal includes generating non-overlap timing between rise times and between fall times of the high-side control signal and the low-side control signals when toggling the output voltage level of the output voltage signal.

18. The method of claim 16 , further comprising delaying the generating the low-side control signal.

19. The method of claim 16 , wherein generating the edge-controlled signal includes coupling the pull-down control current to the edge-controlled signal when a switch for activating the pull-up device is activated, wherein the pull-down control current is relatively greater than a pull-up control current.

20. The method of claim 19 , wherein generating the edge-controlled signal includes coupling a speed-up capacitor to the switch controlling the pull-up device, the pull-down control current being proportional to a ratio of a capacitance of the speed-up capacitor and a parasitic capacitance.

21. The method of claim 20 , further comprising actively discharging the speed-up capacitor in response to the input signal.

22. An integrated circuit, comprising:

a plurality of semiconductor devices; and

a level-shifting circuit, the level-shifting circuit comprising:

a current mirror configured to mirror a pull-up control current onto an edge-controlled signal;

a control gate comprising operably coupled to the current mirror and between the edge-controlled signal and a pull-down control current, and configured to pull-down the edge-controlled signal in response to an inverted input signal on the control gate;

a high-side inverting buffer operably coupled to the current mirror between the edge-controlled signal and a high-side control signal;

a low-side buffer configured for driving a low-side control signal responsive to the inverted input signal; and

an output circuit operably coupled to the high-side inverting buffer and the low-side buffer, wherein the output circuit further comprises:

a pull-up transistor operably coupled to the high-voltage source and configured for pulling up a voltage on an output signal in response to the high-side control signal; and

a pull-down transistor operably coupled in series between the low-voltage source and the pull-up transistor, wherein the pull-down transistor is configured for pulling down the voltage on the output signal in response to the low-side control signal.

23. The integrated circuit of claim 22 , wherein the high-side control signal and the low-side control signal have non-overlap timing of the rise times of the high-side control signal and the low-side control signal and of the fall times of the high-side control signal and the low-side control signal when alternatingly pulling up and pulling down the voltage on the output signal.

24. The integrated circuit of claim 22 , wherein:

the current mirror, the high-side inverting buffer, and the low-side buffer each comprise at least one low-voltage device, wherein the at least one low-voltage device of the high-side inverting buffer is configured to operate in a high-side low-voltage swing between a high-voltage source and a differential voltage less than the high-voltage source, and the at least one low-voltage device of the low-side buffer is configured to operate in a low-side low-voltage swing between a low-voltage source and a differential voltage above the low-voltage source; and

the control gate and the output circuit each comprise at least one high-voltage device configured for operation at voltages above a safe Vgs voltage of the low-voltage devices.