Digitally controlled system on-chip (SOC) clock generator
View Patent ↗A clock generator includes a clock circuit and a voltage-controlled oscillator in a phase-locked loop. The clock circuit monitors input clock signals and selects one of the input clock signals based on characteristics of the input clock signals. The voltage-controlled oscillator generates a reference clock signal based on the selected clock signal. The clock circuit also includes synthesizers for generating clock signals, each of which has a frequency being a non-integer multiple of a frequency of the reference clock signal. Additionally, the clock circuit individually offsets the clock signals generated by the synthesizers relative to the reference clock signal. The clock generator is capable of switching the input clock signal during operation of the clock generator while maintaining the reference clock signal. Further, the clock generator is programmable to control operation of the clock circuit.
1. A clock generator comprising:
a voltage-controlled oscillator configured to generate a reference clock signal having a frequency based on an input clock signal; and
a clock circuit coupled to the voltage-controlled oscillator and configured to form a first phase-locked loop in conjunction with the voltage-controlled oscillator, the clock circuit comprising:
a first synthesizer coupled to the voltage-controlled oscillator and configured to generate a first fractional clock signal based on the reference clock signal, the first fractional clock signal having a frequency being a non-integer multiple of the frequency of the reference clock signal; and
a first output controller coupled to the first synthesizer and configured to generate a first output clock signal by synchronizing the first fractional clock signal with the reference clock signal and introducing an offset in the first output clock signal relative to the reference clock signal.
2. The clock generator of claim 1 , further comprising a first divider coupled to the voltage-controlled oscillator and configured to generate a second output clock signal having a frequency based on the reference clock signal, the frequency of the reference clock signal being an integer multiple of the frequency of the second output clock signal, wherein the first output controller is further configured to synchronize the first fractional clock signal with the reference clock signal by synchronizing the first fractional clock signal with the second output clock signal.
3. The clock generator of claim 1 , wherein the clock circuit further comprises a clock monitor coupled to the first phase-locked loop and configured to monitor a plurality of input clock signals for identifying frequency variations and loss in the plurality of clock signals and select the input clock signal from the plurality of input clock signals based on the frequency variations and the loss.
4. The clock generator of claim 1 , wherein the first phase-locked loop comprises a digital filter.
5. The clock generator of claim 4 , wherein the digital filter comprises a digital signal processor configured to determine a bandwidth of the reference clock signal.
6. The clock generator of claim 4 , wherein the digital filter comprises a digital signal processor configured to determine a damping of the reference clock signal.
7. The clock generator of claim 1 , wherein the first synthesizer is a cascade fraction synthesizer.
8. The clock generator of claim 1 , wherein the clock circuit is embodied in an integrated circuit.
9. The clock generator of claim 8 , wherein the voltage-controlled oscillator is a voltage-controlled crystal oscillator external of the integrated circuit.
10. The clock generator of claim 9 , wherein the voltage-controlled crystal oscillator is a voltage-controlled SAW oscillator.
11. The clock generator of claim 1 , further comprising:
a system controller configured to generate a control signal indicating a feedback clock signal of the first phase-locked loop;
a second synthesizer coupled to the voltage-controlled oscillator and configured to generate a second fractional clock signal based on the reference clock signal, the second fractional clock signal having a frequency being a non-integer multiple of the frequency of the reference clock signal;
a second output controller coupled to the second synthesizer and configured to generate a third output clock signal by synchronizing the second fractional clock signal with the reference clock signal and introducing an offset in the third output clock signal relative to the reference clock signal;
a second divider coupled to the first synthesizer and configured to generate a first divided clock signal having a frequency based on the first fractional clock signal, the first fractional clock signal having a frequency being an integer multiple of the frequency of the first divided clock signal;
a third divider coupled to the second synthesizer and configured to generate a second divided clock signal having a frequency based on the second fractional clock signal, the second fractional clock signal having a frequency being an integer multiple of the frequency of the second divided clock signal; and
a multiplexer coupled to the second divider, the third divider, and the first phase-locked loop, the multiplexer configured to select either the first divided clock signal or the second divided clock signal as the feedback clock signal based on the control signal and provide the feedback clock signal to the first phase-locked loop.
12. The clock generator of claim 1 , further comprising
a system controller configured to generate a control signal indicating a feedback clock signal of the first phase-locked loop;
a second phase-locked loop coupled to the voltage-controlled oscillator and configured to generate a non-fractional clock signal based on the reference clock signal, the non-fractional clock signal having a frequency being an integer multiple of the frequency of the reference clock signal; and
a third output controller coupled to the second phase-locked loop and configured to generate a fourth output clock signal by synchronizing the non-fractional clock signal with the reference clock signal and introducing an offset in the fourth output clock signal relative to the reference clock signal;
a second divider coupled to the first synthesizer and configured to generate a first divided clock signal having a frequency based on the first fractional clock signal, the first fractional clock signal having a frequency being an integer multiple of the frequency of the first divided clock signal;
a fourth divider coupled to the second phase-locked loop and configured to generate a third divided clock signal having a frequency based on the non-fractional clock signal, the non-fractional clock signal having a frequency being an integer multiple of the frequency of the third divided clock signal; and
a multiplexer coupled to the second divider, the fourth divider, and the first phase-locked loop, the multiplexer configured to select either the first divided clock signal or the third divided clock signal as the feedback clock signal based on the control signal and provide the feedback clock signal to the first phase-locked loop.
13. A method of generating clock signals, the method comprising:
generating a control signal based on an input clock signal;
generating a reference clock signal having a frequency based on the control signal;
generating a first fractional clock signal based on the reference clock signal, the first fractional clock signal having a frequency being a non-integer multiple of the frequency of the reference clock signal; and
generating a first output clock signal by synchronizing the first fractional clock signal with the reference clock signal and introducing an offset in the first output clock signal relative to the reference clock signal.
14. The method of claim 13 , further comprising
generating a second fractional clock signal based on the reference clock signal, the second fractional clock signal having a frequency being a non-integer multiple of the frequency of the reference clock signal; and
generating a third output clock signal by synchronizing the second fractional clock signal with the reference clock signal and introducing an offset in the third output clock signal relative to the reference clock signal.
15. The method of claim 13 , further comprising
generating a non-fractional clock signal based on the reference clock signal, the non-fractional clock signal having a frequency being an integer multiple of the frequency of the reference clock signal; and
generating a fourth output clock signal by synchronizing the non-fractional clock signal with the reference clock signal and introducing an offset in the fourth output clock signal relative to the reference clock signal.
16. The method of claim 13 , further comprising:
monitoring a plurality of clock signals to identify frequency variations and loss in the plurality of clock signals; and
selecting the input clock signal from the plurality of input clock signals based on the identified frequency variations and loss.
17. A clock generator comprising:
means for generating a control signal based on an input clock signal;
means for generating a reference clock signal based on the control signal;
means for generating a first fractional clock signal based on the reference clock signal, the first fractional clock signal having a frequency being a non-integer multiple of the frequency of the reference clock signal; and
means for generating a first output clock signal by synchronizing the first fractional clock signal with the reference clock signal and introducing an offset in the first output clock signal relative to the reference clock signal.
18. The clock generator of claim 17 , further comprising:
means for generating a second fractional clock signal based on the reference clock signal, the second fractional clock signal having a frequency being a non-integer multiple of the frequency of the reference clock signal; and
means for generating a third output clock signal by synchronizing the second fractional clock signal with the reference clock signal and introducing an offset in the third output clock signal relative to the reference clock signal.
19. The clock generator of claim 18 , further comprising
means for generating a non-fractional clock signal based on the reference clock signal, the non-fractional clock signal having a frequency being an integer multiple of the frequency of the reference clock signal; and
means for generating a fourth output clock signal by synchronizing the non-fractional clock signal with the reference clock signal and introducing an offset in the fourth output clock signal relative to the reference clock signal.
20. The clock generator of claim 17 , further comprising:
means for monitoring a plurality of clock signals to identify frequency variations and loss in the plurality of clock signals; and
means for selecting the input clock signal from the plurality of input clock signals based on the frequency variations and loss.