Patent Assignment
Reel/Frame 018908/0692
Assignment of Assignor's Interest
Recorded: 2007-01-23
Pages: 6
Assignors
SIGUENZA, OSCAR
Executed: 2007-01-18
BREID, DUANE
Executed: 2007-01-22
SLUSS, GENE
Executed: 2007-01-22
SHERLEKAR, DEEPAK
Executed: 2007-01-18
COLWELL, MIKE
Executed: 2007-01-18
Assignee
VIRAGE LOGIC CORPORATION
47100 BAYSIDE PARKWAY, FREMONT, CALIFORNIA, 94538
Covered Property
(1)
Structures and Methods for Optimizing Power Consumption in an Integrated Chip Design
Patent:
8,392,862 →
Application:
11/657,228 →
Related Assignments
(1)
Other recorded transfers of the patent in this record — the chain of ownership.