Patent Assignment
Reel/Frame 025105/0907
Assignment of Assignor's Interest
Recorded: 2010-10-08
Pages: 57
Assignors
VIRAGE LOGIC CORPORATION
Executed: 2010-09-02
VL C.V.
Executed: 2010-09-02
ARC CORES LIMITED
Executed: 2010-09-02
ARC INTERNATIONAL I.P., INC.
Executed: 2010-09-02
ARC INTERNATIONAL INTELLECTUAL PROPERTY, INC.
Executed: 2010-09-02
ARC INTERNATIONAL LIMITED, FORMERLY ARC INTERNATIONAL PLC
Executed: 2010-09-02
ARC INTERNATIONAL (UK) LIMITED
Executed: 2010-09-02
Assignee
SYNOPSYS, INC.
700 EAST MIDDLEFIELD ROAD, MOUNTAIN VIEW, CALIFORNIA, 94043
Covered Properties
(264)
Method and Apparatus for Monotonic Algorithmic Digital-to-Analog and Analog-to-Digital Conversion
Patent:
5,258,759 →
Application:
07/962,451 →
Method and Apparatus For Generating Non-Redundant Symbolic Debug Information In Computer Programs
Patent:
6,178,547 →
Application:
08/080,156 →
Method and Apparatus for Long-Term Multi-Valued Storage in Dynamic Analog Memory
Patent:
5,479,170 →
Application:
08/146,660 →
A Semiconductor Structure for Long Term Learning
Patent:
5,627,392 →
Application:
08/399,966 →
Gate Array Cell Architecture and Routing Scheme
Patent:
5,723,883 →
Application:
08/557,474 →
Three-Terminal Silicon Synaptic Device
Patent:
5,825,063 →
Application:
08/690,198 →
Autozeroing Floating-Gate Amplifier
Patent:
5,875,126 →
Application:
08/721,261 →
Integrated Circuit Cell Architecture and Routing Scheme
Patent:
5,923,059 →
Application:
08/747,858 →
Module-Based Logic Architecture and Design Flow for Vlsi Implementation
Patent:
6,051,031 →
Application:
08/795,580 →
Hole Impact Ionization Mechanism of Hot Electron Injection and Four-Terminal P-Fet Semiconductor Structure for Long-Term Learning
Patent:
5,990,512 →
Application:
08/845,018 →
Integrated Circuit Cell Architecture and Routing Scheme
Patent:
5,898,194 →
Application:
08/853,875 →
A Pmos Analog Eeprom Cell
Patent:
5,898,613 →
Application:
08/882,717 →
Reduced Area Gate Array Cell Design Based on Shifted Placement of Alternate Rows of Cells
Patent:
5,923,060 →
Application:
08/917,006 →
Power and Signal Routing Technique for Gate Array Design
Patent:
6,091,090 →
Application:
08/933,552 →
Method for Implementing a Learning Function
Patent:
5,914,894 →
Application:
09/088,655 →
Autozeroing Floating-Gate Amplifier
Patent:
5,986,927 →
Application:
09/189,595 →
A Pmos Analog Eeprom Cell
Patent:
6,144,581 →
Application:
09/201,327 →
Semiconductor Structure for Long-Term Learning
Patent:
6,125,053 →
Application:
09/201,677 →
Dual Port Memory Device with Vertical Shielding
Patent:
6,084,820 →
Application:
09/226,777 →
Memory Array with a Simultaneous Read or Simultaneous Write Ports
Patent:
6,104,663 →
Application:
09/227,501 →
Data Processing Circuit with Cache Memory and Cache Management Unit for Arranging Selected Storage Location in the Cache Memory for Reuse Dependent on a Pos Ition of Particular Address Relative to Current Address
Patent:
6,226,715 →
Application:
09/306,069 →
Synchronous Memory System with Automatic Burst Mode Switching as a Function of the Selected Bus Master
Patent:
6,457,075 →
Application:
09/313,244 →
Multi-Bank Memory with Word-Line Banking
Patent:
6,084,819 →
Application:
09/347,372 →
Multi-Bank Memory with Word-Line Banking, Bit-Line Banking and I/O Multiplexing Utilizing Tilable Interconnects
Patent:
6,091,620 →
Application:
09/347,955 →
Dual -Height Cell with Variable Width Power Rail Architecture
Patent:
6,838,713 →
Application:
09/351,767 →
Analog Computation Device Using Separated Analog Signals, Each Having a Specified Amount of Resolution, and Signal Restoration Devices
Patent:
6,377,194 →
Application:
09/408,137 →
Method and Apparatus for Managing the Configuration and Functionality of a Semiconductor Design
Patent:
6,862,563 →
Application:
09/418,663 →
System and Method for Testing Multiple Port Memory Devices
Patent:
6,269,036 →
Application:
09/439,837 →
Architecture with Multi-Instance Redundancy Implementation
Patent:
6,363,020 →
Application:
09/455,045 →
Reduced latency row selection circuit and method
Patent:
6,356,503 →
Application:
09/510,692 →
Method and Apparatus for Jump Control in a Pipelined Processor
Patent:
6,560,754 →
Application:
09/523,871 →
Multi-bank memory with word-line banking, bit-line banking and i/o multiplexing utilizing tilable interconnects
Patent:
6,310,817 →
Application:
09/528,660 →
Centrally decoded divided wordline (DWL) memory architecture
Patent:
6,236,618 →
Application:
09/542,033 →
Gate Array Architecture Using Elevated Metal Levels for Customization
Patent:
6,617,621 →
Application:
09/588,802 →
Routing Driven, Metal Programmable Integrated Circuit Architecture with Multiple Types of Core Cells
Patent:
6,445,065 →
Application:
09/588,804 →
Compilable Block Clear Mechanism on Per I/O Basis for High-Speed Memory
Patent:
6,466,504 →
Application:
09/590,619 →
Fast full signal differential output path circuit for high-speed memory
Patent:
6,249,471 →
Application:
09/605,221 →
Self-timed clock circuitry in a multi-bank memory instance using a common timing synchronization node
Patent:
6,282,131 →
Application:
09/671,456 →
Hierarchical sense amp and write driver circuitry for compilable memory
Patent:
6,292,427 →
Application:
09/689,352 →
Pmos Analog Eeprom Cell
Patent:
6,452,835 →
Application:
09/699,059 →
Circuitry for Resetting Memory Without a Write Cycle
Patent:
6,466,470 →
Application:
09/706,314 →
Fast Read/Write Cycle Memory Device Having a Self-Timed Read/Write Control Circuit
Patent:
6,392,957 →
Application:
09/728,377 →
System and Method for Increasing Performance in a Compilable Read-Only Memory (Rom)
Patent:
6,424,556 →
Application:
09/750,949 →
Row and Column Accessible Memory with a Built-in Multiplex
Patent:
6,385,122 →
Application:
09/773,319 →
Memory Interface and Method of Interfacing Between Functional Entities
Difference Engine Method and Apparatus
Method and Apparatus for Processor Code Optimization Using Code Compression
Method and Apparatus for Debugging Programs in a Distributed Environment
Memory Having a Redundancy Scheme to Allow One Fuse to Blow Per Faulty Memory Column
Patent:
6,396,760 →
Application:
09/810,817 →
Power and Frequency Adjustable Uart Device
Method and Apparatus for Implementing a Single Cycle Operation in a Data Processing System
Simultaneous Access and Cache Loading in a Hierarchically Organized Memory Circuit
Patent:
6,886,078 →
Application:
09/886,577 →
Simulation Method and Compiler for Hardware/Software Programming
Method and Apparatus to Change the Amount of Redundant Memory Column and Fuses Associated with a Memory Device
Patent:
6,519,202 →
Application:
09/895,896 →
Method and System Using a Common Reset and a Slower Reset Clock
Method and Apparatus for Trimming High-Resolution Digital-to-Analog Converter
Patent:
6,664,909 →
Application:
09/929,652 →
System for Bus Monitoring Using a Reconfigurable Bus Monitor Which Is Adapted to Report Back to Cpu in Response to Detecting Certain Selected Events
Data Communication Bus Traffic Generator Arrangement
Multi-Bank Memory with Word-Line Banking, Bit-Line Banking and I/O Multiplexing Utilizing Tilable Interconnects
Patent:
6,738,279 →
Application:
09/957,098 →
Apparatus, Method, and System to Allocate Redundant Components
Patent:
7,127,647 →
Application:
09/962,761 →
System and Method for Memory Compiler Characterization
Patent:
7,197,438 →
Application:
09/981,954 →
Low Power Read Circuitry for a Memory Circuit Based on Charge Redistribution Between Bitlines and Sense Amplifier
Patent:
6,473,356 →
Application:
10/002,568 →
Apparatus and Method to Generate a Repair Signature for Repairing a Memory
Patent:
7,237,154 →
Application:
10/083,241 →
System and Method for Memory Characterization
Patent:
6,738,953 →
Application:
10/092,056 →
System and Method for Redundancy Implementation in a Semiconductor Device
Data Processor with Enhanced Instruction Execution and Method
System and Method for Increasing Performance in a Compilable Read-Only Memory (Rom)
Patent:
6,587,364 →
Application:
10/128,441 →
System and Method for Bit Line Sharing
Patent:
6,711,067 →
Application:
10/142,523 →
Embedded Test and Repair Scheme and Interface for Compiling a Memory Assembly with Redundancy Implementation
Patent:
7,093,156 →
Application:
10/144,020 →
Radiation-Hardened Static Memory Cell Using Isolation Technology
Patent:
6,744,661 →
Application:
10/146,523 →
Method and Apparatus for Implementing a Data Processor Adapted for Turbo Decoding
Patent:
6,718,504 →
Application:
10/165,146 →
High Voltage Charge Pump Circuit
Patent:
6,661,278 →
Application:
10/191,779 →
Floating-Gate Semiconductor Structures
Method and Apparatus to Reduce the Amount of Redundant Memory Column and Fuses Associated with a Memory Device
Patent:
6,646,933 →
Application:
10/210,525 →
System and Method for Providing Adjustable Read Margins in a Semiconductor Memory
Patent:
7,114,118 →
Application:
10/216,598 →
Built-In Precision Shutdown Apparatus for Effectuating Self-Referenced Access Timing Scheme
Patent:
6,597,629 →
Application:
10/223,499 →
Memory Cell Sensing with Low Noise Generation
Patent:
6,850,446 →
Application:
10/226,380 →
Apparatus, Method, and System Having a Pin to Activate the Self-Test and Repair Instructions
Patent:
7,149,924 →
Application:
10/236,248 →
Apparatus, Method, and System to Allocate Redundant Components with Subsets of the Redundant Components
Patent:
7,149,921 →
Application:
10/236,555 →
Method and Apparatus for Preventing Overtunneling in Pfet-Based Nonvolatile Memory Cells
Use of Analog-Valued Floating-Gate Transistors for Parallel and Serial Signal Processing
Patent:
7,187,237 →
Application:
10/268,116 →
Semiconductor Memory with Multiple Timing Loops
Patent:
6,711,092 →
Application:
10/279,428 →
Method and Apparatus for Calibration of an Array of Scaled Electronic Circuit Elements
Patent:
6,909,389 →
Application:
10/281,384 →
Electrically-Alterable Non-Volatile Memory Cell
Patent:
6,788,574 →
Application:
10/295,742 →
Methods and Apparatuses for Test Circuitry for a Dual-Polarity Non-Volatile Memory Cell
Patent:
6,992,938 →
Application:
10/313,075 →
Methods and Apparatuses for a Dual-Polarity Non-Volatile Memory Cell
Patent:
7,130,213 →
Application:
10/313,199 →
Processor Apparatus and Methods Optimized for Control Applications
Patent:
7,493,470 →
Application:
10/313,548 →
Methods and Apparatuses for Maintaining Information Stored in a Non-Volatile Memory Cell
Patent:
6,842,375 →
Application:
10/313,650 →
Methods and Apparatus for Compiling Instructions for a Data Processor
Patent:
7,278,137 →
Application:
10/330,632 →
Method and Apparatus for Implementing Decode Operations in a Data Processor
Patent:
7,043,682 →
Application:
10/358,495 →
Methods and Apparatuses for a Rom Memory Array Having a Virtually Grounded Line
Patent:
7,002,827 →
Application:
10/364,261 →
System, Method, and Computer Program Product for Interrupt Scheduling in Processing Communication
Patent:
7,320,044 →
Application:
10/371,681 →
System, Method, and Computer Program Product for Processing Reflective State Machines
Patent:
7,039,772 →
Application:
10/371,829 →
System, Method, and Computer Program Product for Memory Management for Defining Class Lists and Node Lists for Allocation and Deallocation of Memory Blocks
Patent:
6,985,976 →
Application:
10/371,830 →
Methods and Apparatuses for a Rom Memory Array Having Twisted Source or Bit Lines
Patent:
6,853,572 →
Application:
10/377,845 →
Method and Apparatus for Jump Control in a Pipelined Processor
Apparatus and Method for Managing Integrated Circuit Designs
System, Method, and Computer Program Product for Shared Memory Queue
Patent:
7,130,936 →
Application:
10/425,286 →
Differential Floating Gate Nonvolatile Memories
Autozeroing Floating-Gate Amplifier
Patent:
6,958,646 →
Application:
10/447,684 →
Method and Apparatus for Suppressing Spurious Values in a Differential Output Current
Patent:
6,977,527 →
Application:
10/455,261 →
Acoustical Virtual Reality Engine and Advanced Techniques for Enhancing Delivered Sound
Low Distortion Band-Pass Analog to Digital Converter with Feed Forward
Patent:
6,954,159 →
Application:
10/612,829 →
High-Voltage Cmos-Compatible Capacitors
Patent:
6,842,327 →
Application:
10/635,247 →
Interleaved Digital Correction for Mash Delta-Sigma Adc
Patent:
6,873,281 →
Application:
10/652,537 →
Apparatus for Trimming High-Resolution Digital-to-Analog Converter
Patent:
8,102,007 →
Application:
10/661,037 →
Various Methods and Apparatuses for a Command Based Bist for Memories
Patent:
7,290,186 →
Application:
10/664,190 →
Apparatus, Method and Computer Program for Dynamic Slip Control in Real-Time Scheduling
Patent:
7,805,724 →
Application:
10/665,875 →
Method, Computer Program and Apparatus for Operating System Dynamic Event Management and Task Scheduling Using Function Calls
Patent:
7,451,447 →
Application:
10/669,542 →
Use of Analog-Valued Floating-Gate Transistors to Match the Electrical Characteristics of Interleaved and Pipelined Circuits
Methods and Apparatuses That Reduce the Size of a Repair Data Container for Repairable Memories
Patent:
7,415,640 →
Application:
10/684,793 →
System and Method for Testing a Memory
Patent:
7,031,866 →
Application:
10/701,545 →
System and Method for Repairing a Memory
Patent:
7,415,641 →
Application:
10/702,014 →
Various Method and Apparatuses to Route Multiple Power Rails to a Cell
Patent:
7,219,324 →
Application:
10/779,194 →
Wordline-Based Source-Biasing Scheme for Reducing Memory Cell Leakage
Patent:
7,061,794 →
Application:
10/813,419 →
Rewriteable Electronic Fuses
Rewriteable Electronic Fuses
High-Voltage Switches in Single-Well Cmos Processes
Rewriteable Electronic Fuses
Partitioned Source Line Architecture for Rom
Patent:
7,035,129 →
Application:
10/816,763 →
Method and Apparatus for Implementing a Data Processor Adapted for Turbo Decoding
Counteracting Overtunneling in Nonvolatile Memory Cells Using Charge Extraction Control
Pfet Nonvolatile Memory
Methods and Apparatuses for Memory Array Leakage Reduction Using Internal Voltage Biasing Circuitry
Patent:
7,149,142 →
Application:
10/856,191 →
Various Methods and Apparatuses to Preserve a Logic State for a Volatile Latch Circuit
Patent:
7,069,522 →
Application:
10/856,520 →
Native High-Voltage N-Channel Ldmosfet in Standard Logic Cmos
Graded-Junction High-Voltage Mosfet in Standard Logic Cmos
Electrically-Alterable Non-Volatile Memory Cell
Patent:
7,095,076 →
Application:
10/897,185 →
Floating-Gate Semiconductor Structures
Floating-Gate Semiconductor Structures
High-Voltage Cmos-Compatible Capacitors
High-Voltage Cmos-Compatible Capacitors
Method and Apparatus for Programming Single-Poly Pfet-Based Nonvolatile Memory Cells
Comparison of Semiconductor Circuitry Simulations
Patent:
7,219,315 →
Application:
10/937,726 →
High-Voltage Ldmosfet and Applications Therefor in Standard Cmos
Dual-Height Cell with Variable Width Power Rail Architecture
Patent:
7,129,562 →
Application:
10/956,689 →
Memory Cell Sensing with Low Noise Generation
Patent:
7,184,346 →
Application:
11/029,916 →
Analog to Digital Converter Using Analog-Valued Floating-Gate Transistors
Use of Analog-Valued Floating-Gate Transistors for Parallel and Serial Signal Processing
Use of Analog-Valued Floating-Gate Transistors for Parallel and Serial Signal Processing
Use of Analog-Valued Floating-Gate Transistors for Parallel and Serial Signal Processing
Method and System for Securing Data in a Multi-Time Programmable Non-Volatile Memory Device
Patent:
7,142,452 →
Application:
11/077,654 →
Compact Non-Volatile Memory Cell and Array System
Inverter Non-Volatile Memory Cell and Array System
Redundant Non-Volatile Memory Cell
Microprocessor architecture having extendible logic
High Voltage Fet Gate Structure
Method and System for Testing a Dual-Port Memory at Speed in a Stressed Environment
Patent:
7,139,204 →
Application:
11/146,829 →
Method and System for Pre-Charging and Biasing a Latch-Type Sense Amplifier
Patent:
7,263,016 →
Application:
11/147,790 →
Method and System for Accelerated Detection of Weak Bits in an Sram Memory Device
Patent:
7,298,659 →
Application:
11/147,791 →
Multi-Port Memory Utilizing an Array of Single-Port Memory Cells
Patent:
7,251,186 →
Application:
11/147,928 →
Pseudo-Nonvolatile Direct-Tunneling Floating-Gate Device
Patent:
8,076,707 →
Application:
11/224,743 →
Hybrid Non-Volatile Memory
Autozeroing Floating-Gate Amplifier
Patent:
7,102,438 →
Application:
11/257,897 →
Capacitive Level Shifting for Analog Signal Processing
High-Voltage Cmos-Compatible Capacitors
Model Modification Method for Timing Interoperability for Simulating Hardware
Mtp Nvm Elements by-Passed for Programming
Programmable Strobe and Clock Generator
Patent:
7,616,036 →
Application:
11/340,147 →
Fault Tolerant Non Volatile Memories and Methods
Compact Virtual Ground Diffusion Programmable Rom Array Architecture, System and Method
Schottky Junction Diode Devices in Cmos with Multiple Wells
Schottky Junction Diode Devices in Cmos
Various Methods and Apparatuses to Preserve a Logic State for a Volatile Latch Circuit
System and Method for Testing a Memory
Use of Analog-Valued Floating-Gate Transistors for Parallel and Serial Signal Processing
Rom with a Partitioned Source Line Architecture
Method and Apparatus for Implementing Decode Operations in a Data Processor
Method and Apparatus for Processor Code Optimization Using Code Compression
Source-Biased Sram Cell with Reduced Memory Cell Leakage
Patent:
7,692,964 →
Application:
11/451,043 →
Graded Junction High Voltage Semiconductor Device
Input-Output Device Testing
System and Method for Compiling a Memory Assembly with Redundancy Implementation
Methods and Apparatuses for Test Methodology of Input-Output Circuits
Patent:
7,598,726 →
Application:
11/510,035 →
Reduced Area High Voltage Switch for Nvm
Input-Output Device Testing Including Embedded Tests
Patent:
7,653,849 →
Application:
11/520,200 →
Input-Output Device Testing Including Voltage Tests
Patent:
8,032,805 →
Application:
11/520,276 →
Methods and Apparatuses for External Voltage Test of Input-Output Circuits
Patent:
7,853,847 →
Application:
11/520,282 →
Input-Output Device Testing Including Initializing and Leakage Testing Input-Output Devices
Patent:
8,032,806 →
Application:
11/520,344 →
Methods and Apparatuses for External Delay Test of Input-Output Circuits
Patent:
7,590,902 →
Application:
11/520,423 →
Input-Output Device Testing Including Delay Tests
Patent:
7,779,319 →
Application:
11/520,480 →
Methods and Apparatuses for External Test Methodology and Initialization of Input-Output Circuits
Patent:
7,856,581 →
Application:
11/520,530 →
System and Method for Providing Adjustable Read Margins in a Semiconductor Memory
Patent:
7,458,005 →
Application:
11/524,691 →
Method and Apparatus for Programming Single-Poly Pfet-Based Nonvolatile Memory Cells
Method and Apparatus for Programming Single-Poly Pfet-Based Nonvolatile Memory Cells
Method and Apparatus for Programming Single-Poly Pfet-Based Nonvolatile Memory Cells
Systems and Methods for Accelerating Sub-Pixel Interpolation in Video Processing Applications
Systems and Methods for Performing Deblocking in Microprocessor-Based Video Codec Applications
Microprocessor System and Method for Instruction-Initiated Recording and Execution of Instruction Sequences in a Dynamically Decoupleable Extended Instruction Pipeline
Systolic-Array Based Systems and Methods for Performing Block Matching in Motion Compensation
Methods and Apparatuses for a Sense Amplifier
System and Method for Peak Current Modeling for an Ic Design
Patent:
7,747,425 →
Application:
11/593,729 →
Non-Volatile Memory Cell Circuit with Programming Through Band-to-Band Tunneling and Impact Ionization Gate Current
Non-Volatile Memory with Programming Through Band-to-Band Tunneling and Impact Ionization Gate Current
Packet Ingress/Egress Block and System and Method for Receiving, Transmitting, and Managing Packetized Data
Patent:
8,289,966 →
Application:
11/607,429 →
Generating Hardware Accelerators and Processor Offloads
Patent:
8,127,113 →
Application:
11/607,452 →
Structured Block Transfer Module, System Architecture, and Method for Transferring
Patent:
8,706,987 →
Application:
11/607,474 →
System and Method for Approximating Intrinsic Capacitance of an Ic Block
Structures and Methods for Optimizing Power Consumption in an Integrated Chip Design
Patent:
8,392,862 →
Application:
11/657,228 →
Non-Volatile Memory Devices Having Floating-Gates Fets with Different Source-Gate and Drain-Gate Border Lengths
Counteracting Overtunneling in Nonvolatile Memory Cells
System and Method for Verifying Ip Integrity in System-on-Chip (Soc) Design
Patent:
7,673,264 →
Application:
11/732,900 →
Various Methods and Apparatuses to Route Multiple Power Rails to a Cell
Inverter Non-Volatile Memory Cell and Array System
Architecture, System and Method for Compressing Repair Data in an Integrated Circuit (Ic) Design
One Time Programmable Memory Test Structures and Methods
Patent:
8,122,307 →
Application:
11/768,974 →
Memory Management Unit (Mmu) to Make Only One Time Programmable (Otp) Memory Appear Multiple Times Programmable (Mtp)
Patent:
8,429,375 →
Application:
11/818,757 →
Hybrid Non-Volatile Memory
Electrostatic Discharge Management Apparatus, Systems, and Methods
Patent:
8,022,498 →
Application:
11/837,810 →
Power-On Reset Apparatus, Systems, and Methods
Patent:
7,843,316 →
Application:
11/842,862 →
Memory Modeling Using an Intermediate Level Structural Description
Patent:
7,768,840 →
Application:
11/847,047 →
Pfet Nonvolatile Memory
Apparatuses and Methods for Efficient Power Rail Structures for Cell Libraries
Methods and Apparatus for Compiling Instructions for a Data Processor
Statistical Yield of a System-On-A-Chip
Patent:
7,904,766 →
Application:
11/951,338 →
Radio Frequency Identification Device Electrostatic Discharge Management
Patent:
7,843,032 →
Application:
11/965,307 →
Radio Frequency Identification Device Power-on Reset Management
Patent:
7,872,566 →
Application:
11/965,359 →
Memory Leakage Control Circuit and Method
Inter-Processor Communication Method
Configurable Single Bit/Dual Bits Memory
Patent:
7,719,896 →
Application:
11/981,056 →
Adaptive Programming of Memory Circuit Including Writing Data in Cells of a Memory Circuit
Patent:
7,724,570 →
Application:
11/982,277 →
Methods for Adaptive Programming of Memory Circuit Including Writing Data in Cells of a Memory Circuit
Patent:
7,724,571 →
Application:
11/982,278 →
RFID tag semiconductor chip with memory management unit (MMU) to make only one time programmable (OTP) memory appear multiple times programmable (MTP)
Patent:
8,433,879 →
Application:
12/006,321 →
Rfid Tag Having Non-Volatile Memory Device Having Floating-Gate Fets with Different Source-Gate and Drain-Gate Border Lengths
Radio Frequency (Rfid) Tag Including Configurable Single Bit/Dual Bits Memory
Patent:
7,796,450 →
Application:
12/012,910 →
Rfid Tag with Redundant Non-Volatile Memory Cell
Power Up Circuit
Patent:
8,179,171 →
Application:
12/057,355 →
Multi-Level Non-Volatile Memory Cell with High-Vt Enhanced Btbt Device
Compact Virtual Ground Diffusion Programmable Rom Array Architecture, System and Method
Non Volatile Memory Circuit with Tailored Reliability
Patent:
7,920,423 →
Application:
12/114,574 →
Power Supply Regulation
Patent:
8,004,310 →
Application:
12/125,063 →
High-Voltage Switch Using Three Fets
Patent:
8,098,088 →
Application:
12/143,133 →
Method and Apparatus for Implementing Decode Operations in a Data Processor
Memory Interface and Method of Interfacing Between Functional Entities
Adaptive Video Encoding Apparatus and Methods
System and Method for Repairing a Memory
Various Methods and Apparatuses for Effective Yield Enhancement of Good Chip Dies Having Memories Per Wafer
Pfet Nonvolatile Memory
Patent:
7,894,261 →
Application:
12/239,696 →
Various Methods and Apparatuses for Memory Modeling Using a Structural Primitive Verification for Memory Compilers
Very Low Power Analog Compensation Circuit
Control Circuit for Pvt Conditions of a Module
Electronic Device, Sytem on Chip and Method for Monitoring a Data Flow
Digital Delay Locked Loop Implementation for Precise Control of Timing Signals
Patent:
7,911,873 →
Application:
12/346,854 →
System and Method for Controlling a Dynamic Random Access Memory
Patent:
8,452,920 →
Application:
12/346,856 →
Dynamic Random Access Memory Controller
Patent:
8,601,205 →
Application:
12/346,859 →
System and Method for Improving Access Efficiency to a Dynamic Random Access Memory
Patent:
8,484,411 →
Application:
12/346,860 →
Low Leakage Rom Architecture
Patent:
8,031,541 →
Application:
12/346,862 →
Compact Read Only Memory Cell
Patent:
8,546,251 →
Application:
12/346,866 →
Distributed Table-Driven Power Mode Computation for Controlling Optimal Clock and Voltage Switching
Non-Volatile Memory Cell Circuit with Programming Through Band-to-Band Tunneling and Impact Ionization Gate Current
Non-Volatile Memory Cell with Btbt Programming
Electronic Device with a High Voltage Tolerant Unit
Systems and Methods for Reducing Memory Array Leakage in High Capacity Memories by Selective Biasing
Compact Virtual Ground Diffusion Programmable Rom Array Architecture, System and Method
Method and Apparatus for Managing the Configuration and Functionality of a Semiconductor Design
Verification of Design Information for Controlling Manufacture of a System on a Chip
A Circuit and Method for Switching Voltage
Patent:
8,193,835 →
Application:
12/716,287 →
Fabricating a Gate Oxide
Patent:
8,501,562 →
Application:
12/717,966 →
System and Method for Clock Control for Power-State Transitions
Low-Swing Cmos Input Circuit
Methods and Systems Related to a Configurable Delay Counter Used with Variable Frequency Clocks
Clock Switching Circuits and Methods to Select from Multiple Clock Sources
Clock Generator
Resource Controlling With Dynamic Priority Adjustment
Related Assignments
(6)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Oct 7, 1996
From: DIORIO, CHRISTOPHER J.; MINCH, BRADLEY A.; HASLER, PAUL E.; MEAD, CARVER A.
To: CALIFORNIA INST. OF TECHNOLOGY
Reel/Frame 008168/0466 →
Assignment of Assignor's Interest
Nov 20, 1996
From: MINCH, BRADLEY A.; HASLER, PAUL E.; DIORIO, CHRISTOPHER J.; MEAD, CARVER A.
To: CALIFORNIA INSTITUTE OF TECHNOLOGY
Reel/Frame 008232/0345 →
Assignment of Assignor's Interest
Dec 15, 2006
From: U.S. PHILIPS CORPORATION
To: NXP B.V.
Reel/Frame 018635/0755 →
Assignment of Assignor's Interest
Dec 15, 2006
From: KONINKLIJKE PHILIPS ELECTRONICS N.V.
To: NXP B.V.
Reel/Frame 018635/0787 →
Change of Name
May 2, 2008
From: METAWARE INCORPORATED
To: ARC INTERNATIONAL PROPERTY, INC.
Reel/Frame 020897/0053 →
Assignment of Assignor's Interest
Apr 23, 2010
From: NXP B. V
To: VL C.V.
Reel/Frame 024278/0084 →