Electronic device with a high voltage tolerant unit
View Patent ↗An electronic device is provided with a high-voltage tolerant circuit. The high-voltage tolerant circuit comprises an input terminal for receiving an input signal (V IN ), a first node (A) and a second node (B), wherein the second node (B) is coupled to an input of a receiver (R). The high-voltage tolerant circuit furthermore comprises a first NMOS transistor (N 1 ) and a first PMOS transistor (P 1 ) coupled in parallel between the input terminal and the second node(B). Furthermore, a second PMOS transistor (P 2 ) is coupled between the input terminal and node A and a second NMOS transistor is coupled with one of its terminals to the first node. The gate of the first NMOS transistor (N 2 ) is coupled to a supply voltage (VDDE). The gate of the first PMOS transistor (P 1 ) is coupled to the first node (A). The gate of the second NMOS transistor (N 2 ) and the gate of the second PMOS transistor (P 2 ) are coupled to the supply voltage (VDDE).
1. An electronic device comprising:
a high voltage tolerant circuit having:
an input terminal for receiving an input signal,
a first node and a second node, wherein the second node is coupled to an input of a receiver,
a first NMOS transistor and a first PMOS transistor coupled in parallel between the input terminal and the second node,
a second PMOS transistor coupled between the input terminal and the first node, and
a second NMOS transistor coupled with one of its terminals to the first node,
wherein the gate of the first NMOS transistor is coupled to a supply voltage,
wherein the gate of the first PMOS transistor is coupled to the first node,
wherein the gate of the second NMOS transistor and the gate of the second PMOS transistor are coupled to the supply voltage,
a third NMOS transistor coupled between the supply voltage and the second node,
wherein the gate of the third NMOS transistor is coupled to the input terminal,
wherein the second terminal of the second NMOS transistor is coupled to the second node.
2. An electronic device comprising:
a high voltage tolerant circuit having:
an input terminal for receiving an input signal,
a first node and a second node, wherein the second node is coupled to an input of a receiver,
a first NMOS transistor and a first PMOS transistor coupled in parallel between the input terminal and the second node,
a second PMOS transistor coupled between the input terminal and the first node, and
a second NMOS transistor coupled with one of its terminals to the first node,
wherein the gate of the first NMOS transistor is coupled to a supply voltage,
wherein the gate of the first PMOS transistor is coupled to the first node,
wherein the gate of the second NMOS transistor and the gate of the second PMOS transistor are coupled to the supply voltage,
a third NMOS transistor coupled between the supply voltage and the second node, wherein the gate of the third NMOS transistor is coupled to the input terminal.
3. The electronic device according to claim 2 , wherein a second terminal of the second NMOS transistor is coupled to the output of the receiver.
4. A circuit comprising:
an input terminal configured to receive an input signal, the input signal changing over a voltage range including a first voltage range and a second voltage range higher than the first voltage range;
an output terminal coupled to an electronic component;
a first transistor between the input terminal and the output terminal and configured to turn on to pass the input signal from the input terminal to the output terminal responsive to a voltage level of the input signal being in the first voltage range;
a second transistor between the input terminal and the output terminal, coupled in parallel to the first transistor, and configured to turn on responsive to the voltage level of the input signal exceeding the second voltage range;
a third transistor in a signal path between the input terminal and the output terminal, the first transistor configured to turn off and the third transistor configured to turn on responsive to the input signal exceeding a supply voltage by at least a threshold voltage level of the third transistor configured to turn off the second transistor and to prevent a voltage level at the output terminal from exceeding a first predetermined voltage limit; and
a fourth transistor in the signal path between the third transistor and the output terminal, the fourth transistor configured to turn off responsive to a voltage level in a node in the signal path between the third transistor and the fourth transistor increasing above a second predetermined voltage limit.
5. The circuit of claim 4 , wherein the first transistor and the fourth transistor are NMOS transistors.
6. The circuit of claim 4 , wherein the second transistor and the third transistor are PMOS transistors.
7. The circuit of claim 4 , wherein:
the first transistor and the second transistor are coupled in parallel between the input terminal and the output terminal,
the third transistor is coupled between the input terminal and the node in the signal path between the third transistor and the fourth transistor,
the fourth transistor having one of its terminals coupled to the node in the signal path between the third transistor and the fourth transistor, wherein the gate of the first transistor is coupled to a supply voltage, the gate of the second transistor is coupled to the node in the signal path between the third transistor and the fourth transistor, and the gate of the fourth transistor and the gate of the third transistor is coupled to the supply voltage, and
a fifth transistor is coupled between the supply voltage and the a first terminal of the fourth transistor, wherein the gate of the fifth transistor is coupled to the input terminal, and the second terminal of the fourth transistor being coupled to the node in the signal path between the third transistor and the fourth transistor.
8. The circuit of claim 4 , wherein the first voltage range is 0 V to the supply voltage minus a threshold voltage level of at least one of the first, fourth, or fifth transistors.
9. The circuit of claim 4 , wherein the second voltage range is the supply voltage minus a threshold voltage level of at least one of the first, fourth, or fifth transistors to the supply voltage plus a threshold voltage level of at least one of the second transistor or the threshold voltage level of the third transistor minus the threshold voltage level of at least one of the first, fourth, or fifth transistors.
10. The circuit of claim 9 , wherein the first predetermined voltage limit is the supply voltage plus the threshold voltage level of at least one of the second transistor or the threshold voltage level of the third transistor.
11. The circuit of claim 9 , wherein the second predetermined voltage limit is the supply voltage minus the threshold voltage level of at least one of the first, fourth, or fifth transistors.
12. A method for providing an interface to multiple voltage domains in an electronic device, the method comprising:
at an input terminal configured to receive an input signal, the input signal changing over a voltage range including a first voltage range and a second voltage range higher than the first voltage range;
passing, using a first transistor between the input terminal and an output terminal, the input signal from the input terminal to the output terminal responsive to a voltage level of the input signal being in the first voltage range;
passing, using a second transistor between the input terminal and the output terminal, the input signal from the input terminal to the output terminal, responsive to the voltage level of the input signal exceeding the second voltage range; and
limiting, by using a third transistor to turn off the second transistor, a voltage level at the output terminal from exceeding a first predetermined voltage limit, the third transistor configured to turn on and the first transistor configured to turn off responsive to the voltage level of the input signal exceeding a supply voltage by at least a threshold voltage level of the third transistor.
13. The method of claim 12 , wherein the first is an NMOS transistors.
14. The method of claim 12 , wherein the second and third transistors are PMOS transistors.
15. The circuit of claim 12 , wherein the first voltage range is 0 V to the supply voltage minus a threshold voltage level of the first transistor.
16. The circuit of claim 12 , wherein the second voltage range is the supply voltage minus a threshold voltage level of the first transistor to the supply voltage plus a threshold voltage level of at least one of the second transistor or the threshold voltage level of the third transistor minus the threshold voltage level of the first transistor.
17. The circuit of claim 16 , wherein the first predetermined voltage limit is the supply voltage plus the threshold voltage level of at least one of the second transistor or the threshold voltage level of the third transistor.
18. The circuit of claim 16 , wherein the second predetermined voltage limit is the supply voltage minus the threshold voltage level of the first transistor.