Power supply regulation
View Patent ↗Power supply regulation. A power supply regulation system includes a transistor through which power is carried. The system also includes a switch connected to a gate of the transistor. Further, the system includes a transmission gate responsive to an input signal to apply a first signal level causing the transistor to enter an ON state in which the transistor carries full power, to apply a second signal level causing the transistor to enter an OFF state in which the transistor carries no power and to apply a third signal level causing the transistor to enter an INTERMEDIATE state in which the amount of power the transistor carries is controlled by the switch.
1. A power supply regulation system comprising:
a power transistor having a source connected to a first terminal of a power supply and a drain connected to a first power input terminal of a load,
a connection between a second terminal of the power supply and a second power input terminal of the load;
a transmission gate having a signal input that receives an on/off power control signal (DS), a first control input that receives a full/reduced power control signal (LS), a second control input that receives a complement (LS-bar) of the full/reduced power control signal, and an output connected to the gate of the power transistor; and
a switching transistor having a source connected to a gate of the power transistor, a drain connected to the drain of the power transistor, and a gate connected to receive the complement of the full/reduced power control signal,
whereby, when the full/reduced power control signal assumes a logic level corresponding with full power control, the transmission gate couples the on/off power control signal to the gate of the power transistor and the switching transistor is switched off, and when the full/reduced power control signal assumes a logic level corresponding with reduced power, the transmission gate output goes to a high-impedance state and the switching transistor causes the power transistor to enter a resistive state that conducts reduced power from the power supply to the load.
2. A system as in claim 1 wherein:
the power transistor comprises a PMOS transistor;
the source of the power transistor is connected to a positive terminal of the power supply; and
the switching transistor comprises a PMOS transistor.
3. A system as in claim 1 wherein:
the power transistor comprises an NMOS transistor;
the source of the power transistor is connected to a negative terminal of the power supply; and
the switching transistor comprises an NMOS transistor.
4. A system as in claim 1 wherein the transmission gate comprises a PMOS transistor and an NMOS transistor each having a drain connected to a source of the other.