Method and apparatus for programming single-poly pFET-based nonvolatile memory cells
View Patent ↗Methods and apparatuses for programming a single-poly pFET-based nonvolatile memory cell bias the cell so that band-to-band tunneling (BTBT) is induced and electrons generated by the BTBT are injected onto a floating gate of the cell. Following a predetermined event, the single-poly pFET is biased to induce impact-ionized hot-electron injection (IHEI). The predetermined event may be, for example, the expiration of a predetermined time period or a determination that a channel has been formed by the BTBT injection process that is sufficiently conducting to support IHEI. Employing BTBT permits a previously overerased or stuck bit to be “unstuck” or “removed” and thus be made usable (i.e., able to be programmed) again.
1. A method for programming a single-poly pFET-based nonvolatile memory cell, comprising:
providing a single-poly pFET having a drain, a source and a floating gate;
applying a reverse-bias voltage across a drain junction of said single-poly pFET, said reverse-bias voltage having a value sufficient to induce band-to-band tunneling (BTBT);
injecting electrons generated by the BTBT onto the floating gate;
upon a conducting channel being formed between the source and drain sufficient to support impact-ionized hot-electron injection (IHEI), biasing the single-poly pFET to induce IHEI;
injecting electrons generated by IHEI onto the floating gate; and
maintaining IHEI until a desired floating-gate voltage is obtained.
2. The method of claim 1 , wherein the single-poly pFET-based nonvolatile memory cell has a stuck bit prior to applying the reverse bias to induce BTBT.
3. The method of claim 2 , wherein the induced BTBT is employed to remove the stuck bit.
4. The method of claim 1 , wherein the single-poly pFET-based nonvolatile memory cell had been previously overerased prior to biasing the single-poly pFET to induce BTBT.
5. The method of claim 1 , wherein the induced BTBT is employed to remove the overerased condition.
6. A programming apparatus for programming a single-poly pFET-based nonvolatile memory cell having a single-poly pFET including a drain, a source and a floating gate, said apparatus comprising:
a switch having a switch control input, said switch operable to couple either a band-to-band tunneling (BTBT) voltage or an impact-ionized hot-electron injection (IHEI) voltage to the drain of the single-poly pFET; and
a switch controller configured to provide a switch control signal to the switch control input, said switch control signal causing said switch to alternate from coupling the BTBT voltage to the drain of the single-poly pFET and coupling the IHEI voltage to the drain of the single-poly pFET.
7. The programming apparatus of claim 6 , wherein during early alternations between coupling the BTBT voltage and the IHEI voltage, BTBT dominates over IHEI and is employed to inject electrons onto the floating gate.
8. The programming apparatus of claim 7 , wherein during said early alternations BTBT is employed to form a channel capable of supporting IHEI.
9. The programming apparatus of claim 7 , wherein during said early alternations electrons generated by BTBT and injected onto the floating gate cause a stuck bit of the single-poly pFET-based nonvolatile memory cell to be removed.
10. The programming apparatus of claim 7 , wherein during said early alternations electrons generated by BTBT and injected onto the floating gate cause an overerased condition of the single-poly pFET-based nonvolatile memory cell to be removed.