Method and apparatus for programming single-poly pFET-based nonvolatile memory cells
View Patent ↗Methods and apparatuses for programming a single-poly pFET-based nonvolatile memory cell bias the cell so that band-to-band tunneling (BTBT) is induced and electrons generated by the BTBT are injected onto a floating gate of the cell. Following a predetermined event, the single-poly pFET is biased to induce impact-ionized hot-electron injection (IHEI). The predetermined event may be, for example, the expiration of a predetermined time period or a determination that a channel has been formed by the BTBT injection process that is sufficiently conducting to support IHEI. Employing BTBT permits a previously overerased or stuck bit to be “unstuck” or “removed” and thus be made usable (i.e., able to be programmed) again.
1. A method for programming a single-poly pFET-based nonvolatile memory cell having a pFET including a drain, a source and a floating gate, said method comprising:
biasing the pFET at a first time to induce band-to-band tunneling (BTBT) and thereby inject electrons onto the floating gate; and
at a second time subsequent to said first time, biasing the pFET to induce impact-ionized hot-electron injection (IHEI) and thereby inject electrons onto the floating gate.
2. The method of claim 1 , further comprising:
at a third time subsequent to said second time, removing the biasing that induced IHEI.
3. The method of claim 2 , wherein said biasing the pFET at a first time includes:
capacitively coupling a relatively high voltage to the floating gate.
4. The method of claim 3 , wherein said biasing the pFET at a first time further includes:
applying a relatively low voltage to the drain of the pFET simultaneously with said capacitive coupling.
5. The method of claim 1 , wherein said biasing the pFET at a first time includes:
capacitively coupling a relatively high voltage to the floating gate.
6. The method of claim 5 , wherein said biasing the pFET at a first time further includes:
applying a relatively low voltage to the drain of the pFET simultaneously with said capacitive coupling.
7. A method for affecting an amount of charge stored on a floating gate of a single-poly pFET having a pFET including a drain, a source and a floating gate, said method comprising:
biasing the pFET at a first time to induce band-to-band tunneling (BTBT) and thereby inject electrons onto the floating gate; and
at a second time subsequent to said first time, biasing the pFET to induce impact-ionized hot-electron injection (IHEI) and thereby inject electrons onto the floating gate.
8. The method of claim 7 , further comprising:
at a third time subsequent to said second time, removing the biasing that induced IHEI.
9. The method of claim 8 , wherein said biasing the pFET at a first time includes:
capacitively coupling a relatively high voltage to the floating gate.
10. The method of claim 9 , wherein said biasing the pFET at a first time further includes:
applying a relatively low voltage to the drain of the pFET simultaneously with said capacitive coupling.
11. The method of claim 7 , wherein said biasing the pFET at a first time includes:
capacitively coupling a relatively high voltage to the floating gate.
12. The method of claim 11 , wherein said biasing the pFET at a first time further includes:
applying a relatively low voltage to the drain of the pFET simultaneously with said capacitive coupling.
13. An apparatus for programming a single-poly pFET-based nonvolatile memory cell having a pFET including a drain, a source and a floating gate, said apparatus comprising:
means for biasing the pFET at a first time to induce band-to-band tunneling (BTBT) and thereby inject electrons onto the floating gate; and
means for biasing the pFET at a second time subsequent to said first time to induce impact-ionized hot-electron injection (IHEI) and thereby inject electrons onto the floating gate.
14. The apparatus of claim 13 , further comprising:
means for removing the biasing that induced IHEI at a third time subsequent to said second time.
15. The apparatus of claim 14 , wherein said means for biasing the pFET at a first time includes:
means for capacitively coupling a relatively high voltage to the floating gate.
16. The apparatus of claim 15 , wherein said means for biasing the pFET at a first time further includes:
means for applying a relatively low voltage to the drain of the pFET simultaneously with said capacitive coupling.
17. The method of claim 13 , wherein said means for biasing the pFET at a first time includes:
means for capacitively coupling a relatively high voltage to the floating gate.
18. The apparatus of claim 17 , wherein said means for biasing the pFET at a first time further includes:
means for applying a relatively low voltage to the drain of the pFET simultaneously with said capacitive coupling.
19. An apparatus for affecting an amount of charge stored on a floating gate of a single-poly pFET having a drain, a source and a floating gate, said apparatus comprising:
means for biasing the pFET at a first time to induce band-to-band tunneling (BTBT) and thereby inject electrons onto the floating gate; and
means for biasing the pFET at a second time subsequent to said first time to induce impact-ionized hot-electron injection (IHEI) and thereby inject electrons onto the floating gate.
20. The apparatus of claim 19 , further comprising:
means for removing the biasing that induced IHEI at a third time subsequent to said second time.
21. The apparatus of claim 20 , wherein said means for biasing the pFET at a first time includes:
means for capacitively coupling a relatively high voltage to the floating gate.
22. The apparatus of claim 21 , wherein said means for biasing the pFET at a first time further includes:
means for applying a relatively low voltage to the drain of the pFET simultaneously with said capacitive coupling.
23. The apparatus of claim 19 , wherein said means for biasing the pFET at a first time includes:
means for capacitively coupling a relatively high voltage to the floating gate.
24. The apparatus of claim 23 , wherein said means for biasing the pFET at a first time further includes:
means for applying a relatively low voltage to the drain of the pFET simultaneously with said capacitive coupling.
25. An apparatus for programming a single-poly pFET-based nonvolatile memory cell having a pFET including a drain, a source and a floating gate, said apparatus comprising:
circuitry for biasing the pFET at a first time to induce band-to-band tunneling (BTBT) and thereby inject electrons onto the floating gate; and
circuitry for biasing the pFET at a second time subsequent to said first time to induce impact-ionized hot-electron injection (IHEI) and thereby inject electrons onto the floating gate.
26. The apparatus of claim 25 , further comprising:
circuitry for removing the biasing that induced IHEI at a third time subsequent to said second time.
27. The apparatus of claim 26 , wherein said circuitry for biasing the pFET at a first time includes:
circuitry for capacitively coupling a relatively high voltage to the floating gate.
28. The apparatus of claim 27 , wherein said circuitry for biasing the pFET at a first time further includes:
circuitry for applying a relatively low voltage to the drain of the pFET simultaneously with said capacitive coupling.
29. The apparatus of claim 25 , wherein said circuitry for biasing the pFET at a first time includes:
circuitry for capacitively coupling a relatively high voltage to the floating gate.
30. The apparatus of claim 29 , wherein said circuitry for biasing the pFET at a first time further includes:
circuitry for applying a relatively low voltage to the drain of the pFET simultaneously with said capacitive coupling.
31. An apparatus for affecting an amount of charge stored on a floating gate of a single-poly pFET having a drain, a source and a floating gate, said apparatus comprising:
circuitry for biasing the pFET at a first time to induce band-to-band tunneling (BTBT) and thereby inject electrons onto the floating gate; and
circuitry for biasing the pFET at a second time subsequent to said first time to induce impact-ionized hot-electron injection (IHEI) and thereby inject electrons onto the floating gate.
32. The apparatus of claim 31 , further comprising:
circuitry for removing the biasing that induced IHEI at a third time subsequent to said second time.
33. The apparatus of claim 32 , wherein said circuitry for biasing the pFET at a first time includes:
circuitry for capacitively coupling a relatively high voltage to the floating gate.
34. The apparatus of claim 33 , wherein said circuitry for biasing the pFET at a first time further includes:
circuitry for applying a relatively low voltage to the drain of the pFET simultaneously with said capacitive coupling.
35. The apparatus of claim 31 , wherein said circuitry for biasing the pFET at a first time includes:
circuitry for capacitively coupling a relatively high voltage to the floating gate.
36. The apparatus of claim 35 , wherein said circuitry for biasing the pFET at a first time further includes:
circuitry for applying a relatively low voltage to the drain of the pFET simultaneously with said capacitive coupling.