IP Library Granted Patent US 7,061,324
Granted Patent B2
US 7,061,324 · App. 11/055,959 · Granted Jun 13, 2006

Use of analog-valued floating-gate transistors for parallel and serial signal processing

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Quick Facts
Patent No.
US 7,061,324
App. No.
11/055,959
Granted
Jun 13, 2006
Kind
B2
Abstract

Analog-valued floating-gate transistors are used as trimmable circuit components for modifying and/or controlling the gain, phase, offset, frequency response, current consumption, and/or transfer function of signal pathways in parallel and/or serial processing circuits in radio frequency, analog, or mixed-signal integrated circuits.

Claims (19)

1. An amplifier circuit, comprising:

a signal input node;

a signal output node;

a p-channel floating gate transistor having a source, a drain and a floating gate; and

an n-channel floating gate transistor having a source, a drain and a floating gate,

wherein the source of the p-channel floating gate transistor is electrically coupled to a source of electrical power of a first electrical potential, the source of the n-channel floating gate transistor is electrically coupled to a source of electrical power of a second electrical potential, the drains of the p-channel floating gate transistor and the n-channel floating gate transistor are electrically coupled to said output node, and the floating gates of the n-channel floating gate transistor and the p-channel floating gate transistor are electrically coupled to said signal input node.

2. The amplifier circuit in accordance with claim 1 , wherein the electrical coupling between the floating gates of the n-channel floating gate transistor, the p-channel floating gate transistor and said signal input node comprise a floating gate transistor having its floating gate electrically coupled to the floating gates of the n-channel floating gate transistor and the p-channel floating gate transistor and its source and drain electrically coupled together and to said signal input node.

3. The amplifier circuit in accordance with claim 1 , wherein the floating gates of the n-channel floating gate transistor and the p-channel floating gate transistor are electrically coupled to said output node with a MOSCAP having a MOSCAP floating gate.

4. The amplifier circuit in accordance with claim 3 , further comprising means for injecting electrons on to said MOSCAP floating gate.

5. The amplifier circuit in accordance with claim 4 , further comprising means for tunneling electrons off of said MOSCAP floating gate.

6. The amplifier circuit in accordance with claim 5 , wherein the electrical coupling between the floating gates of the n-channel floating gate transistor, the p-channel floating gate transistor and said signal input node comprises a floating gate transistor having its floating gate electrically coupled to the floating gates of the n-channel floating gate transistor and the p-channel floating gate transistor and its source and drain electrically coupled together and to said signal input node.

7. The amplifier circuit in accordance with claim 6 , wherein:

the floating gates of the n-channel floating gate transistor and the p-channel floating gate transistor are coupled to a first floating gate node.

8. The amplifier circuit in accordance with claim 7 , further comprising:

an injector disposed to inject electrons onto said first floating gate node.

9. The amplifier circuit in accordance with claim 8 , further comprising:

a tunneling junction disposed to remove electrons from said first floating gate node.

10. The amplifier circuit in accordance with claim 9 , wherein the electrical coupling between the floating gates of the n-channel floating gate transistor, the p-channel floating gate transistor and said signal input node comprise a floating gate transistor having its floating gate electrically coupled to the floating gates of the n-channel floating gate transistor and the p-channel floating gate transistor and its source and drain electrically coupled together and to said signal input node.

11. The amplifier circuit in accordance with claim 10 , wherein the floating gates of the n-channel floating gate transistor and the p-channel floating gate transistor are electrically coupled to said output node with a MOSCAP having a MOSCAP floating gate.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 8, 2010
From: VIRAGE LOGIC CORPORATION; VL C.V.; ARC CORES LIMITED; ARC INTERNATIONAL I.P., INC.; ARC INTERNATIONAL INTELLECTUAL PROPERTY, INC.; ARC INTERNATIONAL LIMITED, FORMERLY ARC INTERNATIONAL PLC; ARC INTERNATIONAL (UK) LIMITED
To: SYNOPSYS, INC.
Reel/Frame 025105/0907 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 6, 2008
From: IMPINJ, INC.
To: VIRAGE LOGIC CORPORATION
Reel/Frame 021637/0351 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 10, 2005
From: DIORIO, CHRISTOPHER J.; HUMES, TODD E.; OLIVER, RONALD A.; COLLERAN, WILLIAM T.; COOPER, SCOTT A.
To: IMPINJ, INC.
Reel/Frame 016281/0788 →