Analog to digital converter using analog-valued floating-gate transistors
View Patent ↗Analog-valued floating-gate transistors are used as trimmable circuit components for modifying and/or controlling the gain, phase, offset, frequency response, current consumption, and/or transfer function of signal pathways in parallel and/or serial processing circuits in radio frequency, analog, or mixed-signal integrated circuits.
1. An analog-to-digital converter (ADC), comprising:
a signal input node;
a signal output node;
a plurality N of processing circuits coupled in parallel between said signal input node and a digital encoding logic block, the digital encoding logic block having a plurality N of inputs and an output coupled to said signal output node, said plurality N of processing circuits each having an amplifier circuit coupled between said signal input node and an amplifier output node; and
a corresponding plurality N of comparators coupled respectively between said amplifier output nodes and corresponding inputs to the digital encoding logic block,
wherein at least one said amplifier circuit includes a transistor having a source, a drain and a floating gate, the source of the transistor electrically coupled to a source of electrical power, the drain of the transistor electrically coupled to said signal output node, and the floating gate of the transistor electrically coupled to said signal input node, and
wherein at least one said amplifier circuit includes:
a p-channel floating gate transistor having a source, a drain and a floating gate; and
an n-channel floating gate transistor having a source, a drain and a floating gate,
wherein the source of the p-channel floating gate transistor is electrically coupled to a source of electrical power of a first electrical potential, the source of the n-channel floating gate transistor is electrically coupled to a source of electrical power of a second electrical potential, the drains of the p-channel floating gate transistor and the n-channel floating gate transistor are electrically coupled to said amplifier output node, and the floating gates of the n-channel floating gate transistor and the p-channel floating gate transistor are electrically coupled to said signal input node.
2. An analog-to-digital converter (ALDC), comprising:
a signal input node;
a signal output node;
a plurality N of signal processing circuits each having an input and an output and disposed in parallel between said signal input node and a corresponding N inputs to a digital encoding logic block, the digital encoding logic also having an output coupled to said signal output node, at least one of said plurality N of signal processing circuits having an amplifier circuit coupled between said input of said signal processing circuit and said output of said signal processing circuit, each input of said N signal processing circuits coupled to said signal input node and each output of said N signal processing circuits coupled to a corresponding one of said N inputs to said digital encoding logic block; and
wherein at least one said amplifier circuits includes a transistor having a source, a drain and a floating gate, the source of the transistor electrically coupled to a source of electrical power, the drain of the transistor electrically coupled to the output of the signal processing circuit having the amplifier circuit, and the floating gate of the transistor electrically coupled to said signal input node.
3. The analog-to-digital converter of claim 2 , further comprising:
a corresponding plurality N of comparators each coupled respectively between one of said outputs of said signal processing circuits and a corresponding input to the digital encoding logic block.
4. The analog-to-digital converter of claim 3 , further comprising:
a gain input node associated with the at least one amplifier circuit.
5. The analog-to-digital converter of claim 3 , further comprising:
an offset input node associated with the at least one amplifier circuit.
6. The analog-to-digital converter of claim 2 , further comprising:
a gain input node associated with the at least one amplifier circuit.
7. The analog-to-digital converter of claim 2 , further comprising:
an offset input node associated with the at least one amplifier circuit.
8. An analog-to-digital converter (ADC), comprising:
a signal input node;
a signal output node;
a plurality N of signal processing circuits each having an input and an output and disposed in parallel between said signal input node and a corresponding N inputs to a digital encoding logic block, the digital encoding logic also having an output coupled to said signal output node, at least one of said plurality N of signal processing circuits having an amplifier circuit coupled between said input of said signal processing circuit and said output of said signal processing circuit, each input of said N signal processing circuits coupled to said signal input node and each output of said N signal processing circuits coupled to a corresponding one of said N inputs to said digital encoding logic block; and
wherein at least one said amplifier circuit includes:
a p-channel floating gate transistor having a source, a drain and a floating gate; and
an n-channel floating gate transistor having a source, a drain and a floating gate,
wherein the source of the p-channel floating gate transistor is electrically coupled to a source of electrical power of a first electrical potential, the source of the n-channel floating gate transistor is electrically coupled to a source of electrical power of a second electrical potential, the drains of the p-channel floating gate transistor and the n-channel floating gate transistor are electrically coupled to the output of the signal processing circuit having the amplifier circuit, and the floating gates of the n-channel floating gate transistor and the p-channel floating gate transistor are electrically coupled to said signal input node.
9. The analog-to-digital converter of claim 8 , further comprising:
a corresponding plurality N of comparators each coupled respectively between one of said outputs of said signal processing circuits and a corresponding input to the digital encoding logic block.
10. The analog-to-digital converter of claim 9 , further comprising:
a gain input node associated with the at least one amplifier circuit.
11. The analog-to-digital converter of claim 9 , further comprising:
an offset input node associated with the at least one amplifier circuit.
12. The analog-to-digital converter of claim 8 , further comprising:
a gain input node associated with the at least one amplifier circuit.
13. The analog-to-digital converter of claim 8 , further comprising:
an offset input node associated with the at least one amplifier circuit.