Adaptive programming of memory circuit including writing data in cells of a memory circuit
View Patent ↗Adaptive programming methods and supportive device architecture for memory devices are provided. Methods include partitioning words into variable length segments. More particularly, methods include receiving a word of data, parsing the word into a plurality of write-subsets, where the size of the write-subsets depends on values of the data and constraints that are specific to the memory circuit, and writing the data in cells of the memory circuit, one write-subset at a time. A memory device includes a digital controller capable of parsing words into a plurality of write-subsets, where the length of write-subsets are depending on values of the data and constraints that are specific to the memory device.
1. A memory circuit, comprising:
cells for storing data;
an input for receiving a word of data to be stored; and
a digital controller for parsing the word into a plurality of write-subsets, a certain one of the write-subsets having a size depending on values of the data of the certain write-subset,
wherein each datum has a value selected from one of 0 and 1,
wherein the size of the write-subset is characterized by an operative number (N) of data bits having a value of 1,
wherein at least two of the write-subsets have the same N, and
wherein the two write-subsets with the same N are further of unequal length.
2. The memory circuit of claim 1 , wherein the memory circuit is a Non-Volatile Memory (NVM) circuit.
3. The memory circuit of claim 1 , wherein the memory circuit is a volatile memory circuit.
4. The memory circuit of claim 1 , wherein the size of the write-subset further depends on a constraint that is specific to the memory circuit.
5. The memory circuit of claim 1 , wherein some of the received data are not stored.
6. The memory circuit of claim 1 , wherein N equals 1.
7. The memory circuit of claim 1 , wherein the controller further determines N from a physical constraint.
8. The memory circuit of claim 7 , wherein the physical constraint relates to an operating temperature of the memory circuit.
9. The memory circuit of claim 7 , wherein the physical constraint relates to a supply voltage of the memory circuit.
10. The memory circuit of claim 7 , wherein the physical constraint is at least one of memory circuit specific constraints selected from a group including a charge pump capacity, a row size, and a cost of writing “0”.
11. The memory circuit of claim 10 , wherein the circuit specific constraint is obtained from architectural configuration data of the memory circuit.
12. The memory circuit of claim 11 , wherein the architectural configuration data is stored in specific ones of the cells.
13. The memory circuit of claim 1 , wherein the controller further adjusts one of the write-subsets to overcome a constraint, prior to writing.
14. The memory circuit of claim 13 , wherein adjusting is performed so as to skip cells where a value of 1 is already stored.
15. The memory circuit of claim 13 , wherein adjusting is performed so as to move at least one data bit that causes a sequence constraint violation to a different write-subset.
16. The memory circuit of claim 1 , wherein the digital controller includes a sequence controller and a subset pointer.
17. A host device, comprising:
an operative circuit; and
a memory circuit, comprising:
cells for storing data for use by the operative circuit;
an input for receiving a word of data to be stored; and
a digital controller for parsing the word into a plurality of write-subsets, a certain one of the write-subsets having a size depending on values of the data of the certain write-subset,
wherein each datum has a value selected from one of 0 and 1,
wherein the size of the write-subset is characterized by an operative number (N) of data bits having a value of 1,
wherein at least two of the write-subsets have the same N, and wherein the two write-subsets with the same N are further of unequal length.
18. The host device of claim 17 , wherein the memory circuit is a Non-Volatile Memory (NVM) circuit.
19. The host device of claim 17 , wherein the memory circuit is a volatile memory circuit.
20. The host device of claim 17 , wherein the digital controller includes a sequence controller and a subset pointer.