Floating-gate semiconductor structures
View Patent ↗Hot-electron injection driven by hole impact ionization in the channel-to-drain junction of a p-channel MOSFET provides a new mechanism for writing a floating-gate memory. Various pFET floating-gate structures use a combination of this mechanism and electron tunneling to implement nonvolatile analog memory, nonvolatile digital memory, or on-line learning in silicon. The memory is nonvolatile because the devices use electrically isolated floating gates to store electronic charge. The devices enable on-line learning because the electron injection and tunneling mechanisms that write the memory can occur during normal device operation. The memory updates and learning are bidirectional because the injection and tunneling mechanisms add and remove electrons from the floating gate, respectively. Because the memory updates depend on both the stored memory and the pFETs terminal voltages, and because they are bidirectional, the devices can implement on-line learning functions.
1. A floating gate device, comprising:
means for sourcing a current;
means for draining a current;
means for channeling a current between said source means and said drain means;
first means for controllably injecting hot electrons from said channeling means to a means for storing charge; and
second means for controllably transferring electrons from said means for storing charge, the second means including a tunneling junction implemented with a shorted nFET.
2. A floating gate device, comprising:
means for sourcing a current;
means for draining a current;
means for channeling a current between said source means and said drain means;
first means for controllably injecting hot electrons from said channeling means to a means for storing charge; and
second means for controllably transferring electrons from said means for storing charge, the second means including a tunneling junction implemented with a shorted pFET.
3. A floating gate device, comprising:
means for sourcing a current;
means for draining a current;
means for channeling a current between said source means and said drain means;
first means for controllably injecting hot electrons from said channeling means to a means for storing charge; and
second means for controllably transferring electrons from said means for storing charge, the second means including a tunneling junction implemented with a n+ region disposed in an n− well.
4. A floating gate device, comprising:
means for sourcing a current;
means for draining a current;
means for channeling a current between said source means and said drain means;
first means for controllably injecting hot electrons from said channeling means to a means for storing charge;
second means for controllably transferring electrons from said means for storing charge; and
a control capacitor comprising a pFET having its drain, source and well connections shorted together.
5. A floating gate device, comprising:
first means for injecting electrons into a floating gate, said first means including a pFET; and
second means for tunneling electrons from said floating gate,
wherein said second means includes an n+ region disposed in an n− well.
6. The floating gate device in accordance with claim 5 , wherein the n+ region and the pFET are disposed in a first n− well.
7. The floating gate device in accordance with claim 5 , wherein the n+ region and the pFET are disposed, respectively, in a first n− well and a second n− well.
8. A floating gate device, comprising:
first means for injecting electrons into a floating gate, said first means including a pFET; and
second means for tunneling electrons from said floating gate,
wherein said second means includes a shorted nFET.
9. A floating gate device, comprising:
first means for injecting electrons into a floating gate, said first means including a pFET; and
second means for tunneling electrons from said floating gate,
wherein said second means includes a shorted pFET.
10. A floating gate device, comprising:
first means for injecting electrons into a floating gate, said first means including a pFET;
second means for tunneling electrons from said floating gate; and
third means for providing capacitance to said floating gate,
wherein said third means includes a shorted pFET.