Electrically-alterable non-volatile memory cell

1. An electrically-alterable non-volatile memory cell, comprising:

a floating gate, wherein at least 70 percent of the floating gate is N+ doped and one or more partitioned areas of the floating gate are doped P+;

an insulating material having a first side and a second side, the floating gate deposited onto the insulating material; and

a P+ doped region abutted to a N+ doped region, the floating gate surrounded by the P+ doped region abutted to the N+ doped region, the P+ doped region connecting to the first side of the insulating material and the N+ doped region connecting to the second side of the insulating material.

2. The apparatus of claim 1 , wherein at least 90 percent of the floating gate is N+ doped and one or more partitioned areas of the floating gate are doped P+.

3. The apparatus of claim 2 , wherein the floating gate is fabricated from a single layer of polysilicon.

4. The apparatus of claim 2 , wherein the electrically-alterable non-volatile memory cell is operable to program information to be stored in the electrically-alterable non-volatile memory cell with a bias voltage of equal to or less than 9.0 volts.

5. The apparatus of claim 1 , wherein the floating gate is fabricated from a single layer of polysilicon.

6. The apparatus of claim 1 , wherein the electrically-alterable non-volatile memory cell is operable to erase information stored in the electrically-alterable non-volatile memory cell with a bias voltage of equal to or less than 9.0 volts.

7. An embedded memory, comprising:

one or more electrically-alterable non-volatile memory cells, an electrically-alterable non-volatile memory cell including:

a sense mode component to communicate information stored in the electrically-alterable non-volatile memory cell during a read operation;

a charge mode component to facilitate programming and erasing of information stored in the electrically-alterable non-volatile memory cell, the charge mode component including a coupling capacitor in a first well and a tunneling capacitor in a second well; and

a floating gate having at least seventy percent of the floating gate N+ doped and one or more partitioned areas of the floating gate are P+ doped.

8. The embedded memory of claim 7 , wherein the sense mode component comprises a read transistor.

9. The embedded memory of claim 7 , wherein sense mode component is located in a third well.

10. The embedded memory of claim 7 , wherein at least one or more of the electrically-alterable non-volatile memory cells further include

a floating gate; and

a P+ doped region abutted to a N+ doped region, the floating gate surrounded by the P+ doped region abutted to the N+ doped region.

11. The embedded memory of claim 10 wherein the floating gate is partially surrounded by the P+ doped region abutted to the N+ doped region.

12. A memory, comprising:

one or more electrically-alterable non-volatile memory cells, an electrically-alterable non-volatile memory cell including:

a sense mode component to communicate information stored in the electrically-alterable non-volatile memory cell during a read operation;

a charge mode component to operate as a capacitive divider to facilitate programming and erasing of information stored in the electrically-alterable non-volatile memory cell by symmetrical movement of charge; and

a floating gate having at least seventy percent of the floating gate N+ doped and one or more partitioned areas of the floating gate are P+ doped.

13. The memory of claim 12 , wherein the programming and erasing voltages are approximately the same value.

14. The memory of claim 12 , wherein the sense mode component is discreet from the charge mode component.

15. A machine readable medium that stores data representing a memory that includes:

one or more electrically-alterable non-volatile memory cells, an electrically-alterable non-volatile memory cell includes

a sense mode component to communicate information stored in the electrically-alterable non-volatile memory cell during a read operation;

a charge mode component to facilitate programming and erasing of information

stored in the electrically-alterable non-volatile memory cell, the charge mode component including a coupling capacitor in a first well and a tunneling capacitor in a second well; and

a floating gate having at least seventy percent of the floating gate N+ doped and one or more partitioned areas of the floating gate are P+ doped.

16. The machine readable medium of claim 15 , wherein the machine readable medium comprises a memory complier to provide a design for one or more lithographic masks used in fabrication of the embedded memory.

17. The machine readable medium of claim 16 , wherein the design for the one or more lithographic masks are utilized during a Complementary Metal Oxide Semiconductor logic process employing equal to or less than 1.0 micron technology.

18. A machine readable medium that stores data representing an electrically-alterable non-volatile memory cell that includes:

a floating gate, wherein at least 70 percent of the floating gate is N+ doped and one or more partitioned areas of the floating gate are doped P+;

an insulating material having a first side and a second side, the floating gate deposited onto the insulating material; and

a P+ doped region abutted to a N+ doped region, the floating gate surrounded by the P+ doped region abutted to the N+ doped region, the P+ doped region connects to the first side and the N+ doped region connects to the second side.

19. The machine readable medium of claim of claim 18 , wherein the machine readable medium comprises a memory complier to provide a design for one or more lithographic masks used in fabrication of the one or more of the electrically-alterable non-volatile memory cells.

20. The machine readable medium of claim 19 , wherein the design for the one or more lithographic masks are utilized during a Complementary Metal Oxide Semiconductor logic process employing equal to or less than one micron technology.