IP Library Granted Patent US 6,931,524
Granted Patent B2
US 6,931,524 · App. 09/942,129 · Granted Aug 16, 2005

System for bus monitoring using a reconfigurable bus monitor which is adapted to report back to CPU in response to detecting certain selected events

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Quick Facts
Patent No.
US 6,931,524
App. No.
09/942,129
Granted
Aug 16, 2005
Kind
B2
Abstract

An adaptive data communication approach permits communication bus monitoring by using a reconfigurable bus monitor built into the CPU bus structure and adapted to report back to the CPU in response to detecting certain CPU-programmed events. In one particular example embodiment, a circuit arrangement having a CPU circuit communicates with another device over a communication channel while a reconfigurable circuit monitors the communication channel. The CPU circuit configures the reconfigurable circuit for monitoring any of various types of event expected to occur on the communication channel. The reconfigurable circuit collects signals passed on the communication channel and reports back to the CPU circuit when data indicative of the first event type occurs on the communication channel. In response to the data indicative of the monitored event, the CPU circuit reconfigures the reconfigurable circuit to monitor for another event type occurring on the communication channel and thereby permits for an adaptive evaluation of the communication channel. Another aspect of the invention is directed to the CPU redirecting data communication in response to this adaptive evaluation.

Claims (41)

1. In a circuit arrangement having a CPU circuit communicating with another device over a communication channel, a method of monitoring signals on the communication channel, comprising:

providing a reconfigurable circuit coupled to the communication channel;

using the CPU circuit to configure the reconfigurable circuit for monitoring a first event type occurring on the communication channel;

in the reconfigurable circuit, collecting signals passed on the communication channel and reporting back to the CPU circuit data indicative of the first event type occurring on the communication channel; and

in response to the data indicative of the monitored event, using the CPU circuit to reconfigure the reconfigurable circuit to monitor for another event type occurring on the communication channel and, thereafter, collecting and evaluating signals passed on the communication channel for the other event.

2. The method of claim 1 , further including using the CPU circuit to evaluate and redirect data over the communication channel as a function of and in response to the data indicative of the monitored event.

3. The method of claim 1 , wherein the reconfigurable circuit includes a register circuit adapted to respond to configuration data by presenting signals corresponding to expected events to be monitored on the communication channel and further including comparing the collected signals with the signals corresponding to the expected events.

4. The method of claim 3 , further including counting the expected events and interrupting the CPU circuit in response to the collected signals matching the expected signals.

5. The method of claim 1 , further including interrupting the CPU circuit in response to the data indicative of the monitored event detected by the reconfigurable circuit.

6. The method of claim 1 , wherein the reconfigurable circuit includes a programmable processor.

7. The method of claim 1 , wherein providing a reconfigurable circuit adapted to measure at least one event type occurring on the communication channel includes configuring the reconfigurable circuit to count said at least one event.

8. The method of claim 1 , wherein providing a reconfigurable circuit adapted to measure at least one event type occurring on the communication channel includes configuring the reconfigurable circuit to time the duration of said at least one event.

9. The method of claim 1 , wherein the first event type and the other event type are different types of events occurring on the communication channel.

10. The method of claim 1 , wherein the first event type and the other event type are the same types of events occurring on the communication channel.

11. The method of claim 1 , further including using the CPU circuit to evaluate the data indicative of the monitored event type before reconfiguring the reconfigurable circuit.

12. A circuit arrangement, comprising:

a reconfigurable circuit coupled to the communication channel and adapted to collect signals passed on the communication channel;

a CPU circuit adapted to communicate with another device over a communication channel and adapted to configure the reconfigurable circuit for monitoring a first event type occurring on the communication channel, wherein the reconfigurable circuit is adapted to respond to the CPU circuit by monitoring for the first event type occurring on the communication channel and by reporting back to the CPU circuit data indicative of the first event; and

the CPU circuit further adapted to respond to the data indicative of the monitored event type by reconfiguring the reconfigurable circuit to monitor for another event type occurring on the communication channel and, thereafter, collect and evaluate signals passed on the communication channel for the other event.

13. The circuit arrangement of claim 12 , wherein the reconfigurable circuit includes a counter.

14. The circuit arrangement of claim 12 , wherein the reconfigurable circuit includes a circuit adapted to decode configuration data by presenting expected signals corresponding to events to be monitored on the communication channel and a comparator circuit adapted to compare the collected signals with the expected signals.

15. The circuit arrangement of claim 14 , further including interruption means for interrupting the CPU circuit in response to the collected signals matching the expected signals.

16. The circuit arrangement of claim 12 , further including interruption means for interrupting the CPU circuit in response to the collected signals matching the expected signals.

17. The circuit arrangement of claim 12 , wherein the CPU circuit includes means for polling the reconfigurable circuit to enable the CPU circuit to read the data indicative of the first event.

18. The circuit arrangement of claim 12 , wherein the first event type and the other event type are different types of events occurring on the communication channel.

19. The circuit arrangement of claim 12 , wherein the first event type and the other event type are the same types of events occurring on the communication channel.

20. The circuit arrangement of claim 12 , wherein the CPU circuit is further adapted to evaluate the data indicative of the monitored event.

21. The circuit arrangement of claim 12 , wherein the CPU circuit is further adapted to redirect data over the communication channel as a function of and in response to the data indicative of the monitored event.

22. A circuit arrangement, comprising:

reconfigurable means, coupled to the communication channel, for collecting signals passed on the communication channel;

CPU means for communicating with another device over the communication channel and for configuring the reconfigurable means for monitoring a first event type occurring on the communication channel, the reconfigurable means also for responding to the CPU means by monitoring for the first event type occurring on the communication channel and by reporting back to the CPU means data indicative of the first event; and

the CPU means also for responding to the data indicative of the monitored event type by reconfiguring the reconfigurable means to monitor for another event type occurring on the communication channel and, thereafter, collect and evaluate signals passed on the communication channel for the other event type.

23. A circuit arrangement, comprising:

reconfigurable circuit, coupled to the communication channel, for collecting signals passed on the communication channel;

CPU means for communicating with another device over the communication channel and for configuring the reconfigurable circuit for monitoring a first event type occurring on the communication channel, the reconfigurable circuit also for responding to the CPU means by monitoring for the first event type occurring on the communication channel;

interruption means, coupled to the reconfigurable circuit, for interrupting the CPU circuit in response to the collected signals matching the expected signals; and

the CPU means also for responding to the interruption means by reconfiguring the reconfigurable circuit to monitor for another event type occurring on the communication channel and, thereafter, collect and evaluate signals passed on the communication channel for the other event type.

24. The circuit arrangement of claim 23 , wherein the CPU means includes means for evaluating the data indicative of the monitored event.

25. The circuit arrangement of claim 23 , wherein the CPU means includes means for redirecting data over the communication channel as a function of and in response to the data indicative of the monitored event.

26. The circuit arrangement of claim 23 , wherein the reconfigurable circuit includes multiple comparators for monitoring different events concurrently.

27. The circuit arrangement of claim 26 , further including multiple counters, each of said counters being responsive to a respective one of said multiple comparators.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 8, 2010
From: VIRAGE LOGIC CORPORATION; VL C.V.; ARC CORES LIMITED; ARC INTERNATIONAL I.P., INC.; ARC INTERNATIONAL INTELLECTUAL PROPERTY, INC.; ARC INTERNATIONAL LIMITED, FORMERLY ARC INTERNATIONAL PLC; ARC INTERNATIONAL (UK) LIMITED
To: SYNOPSYS, INC.
Reel/Frame 025105/0907 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 23, 2010
From: NXP B. V
To: VL C.V.
Reel/Frame 024278/0084 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 2006
From: KONINKLIJKE PHILIPS ELECTRONICS N.V.
To: NXP B.V.
Reel/Frame 018635/0787 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2001
From: EHMANN, GREGORY E.; SAXENA, SWATI
To: KONINKLIJKE PHILIPS ELECTRONICS N.V.
Reel/Frame 012132/0433 →