System and method for compiling a memory assembly with redundancy implementation
View Patent ↗In one embodiment, a computer-implemented system for compiling a fuse assembly for a memory is disclosed. The claimed embodiment comprises: means for defining a memory group including at least one memory instance, each memory instance being characterized by its memory configuration data; means for determining number of fuses required for each memory instance based on its configuration data; means for automatically passing fuse information relating to the number of fuses to a fuse compiler; and means for generating, based on the fuse information, a fuse box assembly having a plurality of fuses organized into a set of fuse segments, each segment corresponding to a particular memory instance of the memory group.
1. A computer program product that includes a computer usable medium having computer readable program code for compiling a fuse assembly for a memory, comprising:
program code operable to define a memory group that includes a plurality of memory instances that are functionally related, each memory instance being characterized by its memory configuration data;
program code operable to determine a number of fuses required for each memory instance based on its configuration data;
program code operable to automatically pass fuse information relating to said number of fuses to a fuse compiler; and
program code operable to generate, based on said fuse information, a fuse box assembly for said memory group, said fuse box assembly having a plurality of fuses organized into a set of fuse segments, each segment corresponding to a particular memory instance of said memory group.
2. The computer program product as set forth in claim 1 , wherein said memory configuration data comprises at least one of NW (the number of words), NB (the number of bits) and column MUX information associated with said particular memory instance.
3. The computer program product as set forth in claim 1 , wherein said program code operable to determine the number of fuses required for each memory instance includes program code for computing a fuse equation associated with each particular memory instance of said memory group.
4. The computer program product as set forth in claim 1 , wherein said memory group includes at least one of a static random access memory (SRAM) instance, an electrically programmable read-only memory (EPROM) instance, a dynamic random access memory (DRAM) instance, and a Flash memory instance.
5. A method for facilitating a fuse assembly compiling process associated with a memory architecture, comprising:
defining, via a user interface, a memory group including a plurality of memory instances that are functionally related, each memory instance being characterized by its memory configuration data; and
automatically passing a number of fuses necessary for each memory instance in said memory group to a fuse compiler, wherein said number of fuses required for each memory instance is determined based on its configuration data.
6. The method as set forth in claim 5 , wherein said memory configuration data comprises at least one of NW (the number of words), NB (the number of bits) and column MUX information associated with a particular memory instance.
7. The method as set forth in claim 6 , wherein said number of fuses required for each memory instance is determined based on computing a fuse equation associated with each particular memory instance of said memory group.
8. The method as set forth in claim 7 , wherein said memory group includes at least one of a static random access memory (SRAM) instance, an electrically programmable read-only memory (EPROM) instance, a dynamic random access memory (DRAM) instance, and a Flash memory instance.