Apparatus and method for managing integrated circuit designs
View Patent ↗Apparatus and methods for integrated circuit (IC) design, including management of the configuration, design parameters, and functionality of a design in which custom instructions or other design elements may be controlled by the designer. In one exemplary embodiment, a computer program rendered in an object-oriented language implementing the aforementioned methods for designing user-customized digital processors is disclosed. Design iteration, component encapsulation, use of human-readable file formats, extensible dynamic GUIs and tool sets, and other features are employed to enhance the functionality and accessibility of the program. Components within the design environment comprise encapsulated objects which contain information relating to interfaces with other components in the design, hierarchy, and other facets of the design process.
1. A computerized system for generating user-configured designs of integrated circuits, comprising:
a user interface adapted to provide and receive information to and from a user, respectively; and
an object-oriented design environment operatively coupled to said user interface and having a plurality of associated design tools, wherein a plurality of components associated with said designs of integrated circuits are represented as objects, at least a portion of said objects being encapsulated and containing information relating to both the interface and build hierarchy associated with its respective design component, said design tools using said information within said objects to build said design, said objects being user-configurable and selectable within said environment via said user interface;
wherein said objects being user configurable comprises adding an extension instruction to said designs of integrated circuits, said extension instruction comprising a mixed length instruction set architecture that utilizes instructions of at least two lengths without a mode switch.
2. The system of claim 1 , wherein said information comprises a maximum memory bus width.
3. The system of claim 1 , wherein said information comprises at least one Java script.
4. The system of claim 1 , wherein said plurality of components comprise a processor core and an extension instruction, said information comprising HDL that must be added to HDL associated with said core for said extension.
5. The system of claim 1 , wherein said information comprises a script which is evaluated at runtime to retrieve said interfaces and said build hierarchy.