Methods and apparatuses for test methodology of input-output circuits
View Patent ↗Various methods and apparatuses are described for a system that includes some on-chip components, e.g., I/Os, test processors, soft wrappers, etc., an external testing unit that provides Parametric Measurement Unit (PMU) capability, a Device Interface Board (DIB) that includes resistors between the chip and the external tester, and various tests performed on the I/Os by the on-chip testing logic and external testing unit facilitated through the DIB.
1. An apparatus, comprising:
a device interface board having a first plurality of connection paths to connect two or more Input-Output (I/O) circuits in a first group of I/O circuits to a first pin on a tester that is external to a platform containing all of the I/O circuits, where the first pin to couple to a first Parametric Measurement Unit (PMU), wherein the first plurality of connection paths connects the two or more I/O circuits in the first group of I/O circuits to the first PMU via its own resistor and the device interface board has a switch to connect a terminal of all of the resistors coupled to their respective I/O circuit in the first group of I/O circuits to ground.
2. The apparatus of claim 1 , further comprising:
a soft wrapper logic circuit configured to send control signals to enable both pull up and pull down transistors in a first I/O circuit in the first group of I/O circuits and to disable both the pull up and the pull down transistors in the first I/O circuit.
3. The apparatus of claim 2 , wherein the soft wrapper logic circuit also is configured to issue commands to enable and disable an output voltage driver in the first I/O circuit.
4. The apparatus of claim 1 , wherein a first I/O circuit in the first group of I/O circuits has logic configured to support an enable/disable feature for pull-up and pull-down transistors in that I/O circuit.
5. The apparatus of claim 1 , wherein the device interface board further includes a plurality of capacitors and a first I/O circuit in the first group of I/O circuits is connected to its own resistor and its own capacitor on the device interface board.
6. The apparatus of claim 1 , wherein the device interface board further includes a second plurality of connection paths to connect a second group of I/O circuits to a second pin on the tester associated with a second PMU, wherein the second plurality connection path to connect each I/O circuit in the second group of I/O circuits to the second PMU via its own resistor and the two or more resistors for the first group, each resistor associated with its own I/O circuit, connect to the first pin and the two or more resistors in the second group connect to the second pin.
7. A method, comprising:
performing at least one of 1) a Direct Current (DC) voltage parameter test and 2) DC current parameter test on each Input-Output (I/O) circuit in a group of I/O circuits connected through its own resistor to a first pin on an external test unit that executes a Parametric Measurement Unit (PMU) function, where a device interface board coupled to the external test unit has a switch to connect a terminal of all of the resistors coupled to their respective I/O circuit in a first group of I/O circuits to ground and the first group has two or more I/O circuits;
determining a DC output voltage level supplied from each I/O circuit in the group of I/O circuits, one I/O circuit at a time by enabling an output driver and a pull up transistor of an individual I/O circuit under test, and measuring a first amount of current flowing to the PMU from the individual I/O circuit under test, and
sequentially repeating this determining of DC output voltage level step for each remaining I/O circuit in the group.
8. The method of claim 7 , further comprising:
disabling an output driver of every I/O circuit in the group of I/O circuits connected to the first pin;
disabling every I/O circuit's pull up and pull down transistors in the group of I/O circuits; and
determining total leakage current from the group of I/O circuits by forcing the first pin that connects the PMU to ground DC voltage potential and measuring a second amount of current flowing from the group of disabled I/O circuits to the PMU.
9. The method of claim 8 , further comprising:
sequentially repeating this determining of DC output voltage level step for each remaining I/O circuit in the group after the below calibration step occurs for the individual I/O circuit under test;
calibrating the determined output DC voltage level supplied from the I/O circuit under test to account for leakage current by subtracting the measured second amount of total leakage current from the measured first amount of current from the individual I/O circuit under test and converting the remainder to a DC output voltage to determine the calibrated output DC voltage level supplied from that I/O circuit under test; and
sequentially testing each remaining I/O circuit in the group by disabling the pull up transistor and the output driver associated with the I/O circuit previously tested and enabling the pull up transistor and output driver of the I/O circuit to be tested.
10. The method of claim 7 , further comprising:
performing a first Direct Current output voltage parameter test on a first I/O circuit in a first plurality of I/O circuits that includes the group of I/O circuits while in parallel performing a second output Direct Current voltage parameter test on a second I/O circuit in a second plurality of I/O circuits.
11. The method of claim 7 , further comprising:
simultaneously performing an input DC voltage test on the group of I/O circuits connected to the first pin on the external test unit that supports the PMU function.
12. The method of claim 11 , wherein the simultaneously performing of the input DC voltage test further includes
disabling an output driver of every I/O circuit in the group of I/O circuits connected to the first pin;
forcing the first pin that supports the PMU to a first input DC voltage potential for all of the I/O circuits in the group of I/O circuits connected to the first pin; and
analyzing test results for all of the I/O circuits in the group that are of a same type and have a substantially similar input DC voltage threshold value by comparing captured logic results of each I/O circuit having the same type and similar input DC voltage threshold to expected results.
13. The method of claim 12 , further comprising:
repeating the above steps for other types of I/O circuits in the group of I/O circuits connected to the first pin that has a different input DC voltage threshold by forcing the first pin that supports the PMU to a second input DC voltage potential rather than the first input DC voltage potential.
14. The method of claim 11 , further comprising:
disabling every I/O circuit's pull up and pull down transistors in the group of I/O circuits;
forming all of the I/O circuits in the group into one or more sub groups, where each group contains I/O circuits that have a same type and have a substantially similar input DC voltage threshold value;
forcing the first pin that supports the PMU to a first input DC voltage potential for all of the I/O circuits in a first sub group; determining a calibrated first input DC voltage potential for all of the I/O circuits in the first sub group by increasing the first input DC voltage potential by a first voltage drop amount across a first resistor between a first I/O circuit in the first subgroup and the first pin;
forcing the first pin that supports the PMU to the calibrated first input DC voltage potential for all of the I/O circuits in the first sub group; and
storing test results from the applied calibrated first input DC voltage potential for all of the I/O circuits in the first sub group.
15. The method of claim 14 , further comprising:
forcing the first pin that supports the PMU to a second input DC voltage potential for all of the I/O circuits in a second sub group;
generating a calibrated second input DC voltage potential for all of the I/O circuits in the second sub group by increasing the second input DC voltage potential by a second voltage drop amount across a second resistor between a second I/O circuit in the second sub group and the first pin;
forcing the first pin that supports the PMU to the calibrated second input DC voltage potential for all of the I/O circuits in the second sub group; and
storing test results from the applied calibrated second input DC voltage potential for all of the I/O circuits in the second sub group.
16. The method of claim 7 , further comprising:
performing also a delay parameter test on each I/O circuit in the group of I/O circuits, all of the I/O circuits at the same time.
17. A machine-readable medium that stores instructions, which when executed by the machine, to generate an instance to perform the method of claim 7 .
18. A machine-readable medium that stores instructions, which when executed by the machine, to generate instructions for a tester, the I/O circuits, and a soft wrapper, to run test sequences recited in the method of claim 7 .
19. A machine-readable medium that stores instructions, which when executed by the machine, to generate instructions for a tester, the I/O circuits, and a soft wrapper, to run test sequences recited in the method of claim 11 .
20. A machine-readable medium that stores instructions, which when executed by the machine, to generate an instance to perform the method of claim 11 .
21. An apparatus, comprising:
a first plurality of Input-Output (I/O) circuits connectable via one or more resistors to a first pin on a tester that is external to the apparatus containing all of the I/O circuits, where the first pin is to couple to a first Parametric Measurement Unit (PMU), wherein a switch connects a terminal to ground for of all of the resistors coupled to their respective I/O circuit in the first plurality of I/O circuits; and
a soft wrapper circuit coupled to the first plurality of I/O circuits, wherein the soft wrapper circuit has logic configured to send control signals to enable as well as disable pull up and pull down transistors in the first plurality of I/O circuits.
22. The apparatus of claim 21 , wherein the soft wrapper circuit has additional logic configured to send control signals for performing an input Direct Current (DC) voltage parameter test simultaneously on each I/O circuit in the first plurality of I/O circuits, and the soft wrapper circuit has additional logic configured to compensate the input DC voltage parameter test based on leakage current from the first plurality of I/O circuits.
23. The apparatus of claim 21 , wherein the soft wrapper circuit has additional logic configured to send control signals to perform an output Direct Current (DC) voltage parameter test on each I/O circuit in the first plurality of I/O circuits by
determining total leakage current from the first plurality of I/O circuits connected to the first pin on the external test unit that supports the PMU function,
determining a DC output voltage level supplied from each I/O circuit in the first plurality of I/O circuits, one I/O circuit at a time, and
calibrating the determined output DC voltage level supplied from each I/O circuit under test.
24. A machine-readable medium that stores instructions, which when executed by the machine, to cause the machine to generate a representation of the apparatus of claim 21 .