High-voltage CMOS-compatible capacitors
View Patent ↗A high-voltage stacked capacitor includes a first capacitor and a second capacitor. Each capacitor includes a first plate having a first semiconductive body and a second plate having a floating electrode. The first and second semiconductive bodies are electrically isolated from each other. The floating electrode includes an intercapacitor node configured to self-adjust to a value less than a working voltage impressed on the stacked capacitor.
1. A method comprising:
in a stacked capacitor having a first capacitor having a first plate comprising a first semiconductive body and a second plate comprising a first floating electrode, and a second capacitor having a first plate comprising a second semiconductive body and a second plate comprising a second floating electrode, the first and second semiconductive bodies being electrically isolated from each other, the first and second floating electrodes being connected together at an intercapacitor node, coupling a first potential to the first electrode;
coupling a second potential to the second electrode, a difference between the first and second potentials comprising a working voltage of the stacked capacitor; and
charging the intercapacitor node to a floating voltage whose value is less than the working voltage.
2. The method of claim 1 , wherein the first and second floating electrodes are only electrically connected to each other and to the intercapacitor node.
3. The method of claim 1 , wherein additional circuit elements are electrically connected to the intercapacitor node, each of the additional circuit elements chosen from a group consisting of: a capacitor, a resistor, a diode, a field-effect transistor, a NFET, a PFET, a MOSCAP, a bipolar-junction transistor, a metal-semiconductor field-effect transistor, a FinFET, a vertical-gate transistor and an insulated-gate transistor.
4. The method of claim 1 , wherein the first and second floating electrodes comprise a material chosen from a group consisting of: polysilicon, semiconductor material and a metal.
5. The method of claim 1 , wherein the first and second semiconductive bodies comprise doped silicon.
6. The method of claim 1 , further comprising self-adjusting the intercapacitor node to a value less than a working voltage impressed on the stacked capacitor.
7. The method of claim 1 , further comprising storing a voltage at the intercapacitor node when electrical power is removed from the stacked capacitor.
8. The method of claim 1 , further comprising: adjusting a floating voltage of first and second floating electrodes to a value less than a working voltage of the stacked capacitor.
9. The method of claim 1 , wherein the first and second capacitors are configured to be further responsive to actions including storing the floating voltage on the floating electrode following removal of the first and second potentials from the stacked capacitor.
10. The method of claim 1 , wherein the first and second capacitors are configured to be responsive to acts including tunneling charge carriers through a dielectric, wherein the dielectric includes a first portion disposed between the first semiconductive body and a corresponding portion of the floating electrode and the dielectric includes a second portion disposed between the second semiconductive body and a corresponding portion of the floating electrode.
11. The method of claim 1 , wherein coupling the first potential to the first electrode and coupling the second potential to the second electrode comprise coupling the first and second potentials to first and second electrodes of the stacked capacitor, and wherein the stacked capacitor comprises a plurality of PFETs, NFETs or MOSCAPs, or any combination thereof coupled to the common intercapacitor node.