System and method for providing adjustable read margins in a semiconductor memory

1. A method of effectuating a self-timed clock loop for access operations in a semiconductor memory device having at least one memory instance, comprising:

configuring a particular access margin value setting, wherein said configuring is dynamically performed by an access margin optimization algorithmic process executed on an Embedded Test and Repair (ETR) processor engine associated with said semiconductor memory device to determine said particular access margin value; and

applying said particular access margin value setting to a reference cell assembly associated with said at least one memory instance for facilitating generation of a self-timed clock signal that is optimized for said at least one memory instance.

2. The method of effectuating a self-timed clock loop for access operations in a semiconductor memory device as set forth in claim 1 , wherein configuring said particular access margin value setting comprises optimization of said access margin value setting in an iterative process.

3. The method of effectuating a self-timed clock loop for access operations in a semiconductor memory device as set forth in claim 1 , wherein said configuring further includes testing said at least one memory instance using a plurality of access margin values.

4. The method of effectuating a self-timed clock loop for access operations in a semiconductor memory device as set forth in claim 1 , wherein said configuring further includes supplying user input to adjust an access margin value.

5. The method of effectuating a self-timed clock loop for access operations in a semiconductor memory device as set forth in claim 1 , further comprising loading a default access margin value setting in a register associated with said at least one memory instance.

6. A system for effectuating a self-timed clock loop for access operations in a semiconductor memory device having at least one memory instance, comprising:

means for configuring a particular access margin value setting, wherein said means for configuring comprises an access martin optimization algorithmic process executed on an Embedded Test and Repair (ETR) processor engine associated with said semiconductor memory device to determine said particular access margin value setting; and

means for applying said particular access margin value setting to a reference cell assembly associated with said at least one memory instance for facilitating generation of a self-timed clock signal that is optimized for said at least one memory instance.

7. The system for effectuating a self-timed clock loop for access operations in a semiconductor memory device as set forth in claim 6 , wherein said means for configuring said particular access margin value setting comprises optimizing the access margin value setting in an iterative process.

8. The system for effectuating a self-timed clock loop for access operations in a semiconductor memory device as set forth in claim 6 , wherein said means for configuring tests said at least one memory instance using a plurality of access margin values.

9. The system for effectuating a self-timed clock loop for access operations in a semiconductor memory device as set forth in claim 6 , wherein said configuring further includes supplying user input to adjust an access margin value.

10. The system for effectuating a self-timed clock loop for access operations in a semiconductor memory device as set forth in claim 6 , further comprising means for loading a default access margin value setting in a register associated with said at least one memory instance.

11. A semiconductor memory device, comprising:

circuitry to generate an internal memory clock based on an external clock supplied thereto, said internal memory clock for providing a timing reference for an access operation with respect to a memory array;

circuitry to generate a self-timed clock signal using a particular access margin value setting for controlling said access operation, wherein said particular access margin value setting is operable to be adjusted; and

circuitry to dynamically configure said particular access margin value setting.

12. The semiconductor memory device as set forth in claim 11 , wherein said circuitry to dynamically configure said particular access margin value setting performs optimization of an access margin value setting in an iterative process.

13. The semiconductor memory device as set forth in claim 12 , wherein said iterative process performs read access operations at a plurality of access margin value settings to determine an optimal setting.