Counteracting overtunneling in nonvolatile memory cells
View Patent ↗Methods and apparatuses prevent overtunneling in nonvolatile floating gate memory (NVM) cells. An individual cell includes a circuit with a transistor that has a floating gate that stores charge, and a capacitor structure for extracting charge from the gate, such as by tunneling. A counteracting circuit prevents extracting charge from the floating gate beyond a threshold, therefore preventing overtunneling or correcting for it. In one embodiment, the counteracting circuit supplies electrons to the floating gate, to compensate for tunneling beyond a point. In another embodiment, the counteracting circuit includes a switch, and a sensor to trigger the switch when the appropriate threshold is reached. The switch may be arranged in any number of suitable ways, such as to prevent a high voltage from being applied to the capacitor structure, or to prevent a power supply from being applied to a terminal of the transistor or to a well of the transistor.
1. A circuit comprising:
a first transistor with a first floating gate;
a first capacitor structure for extracting charge from the first gate;
a second transistor with a second floating gate;
a second capacitor structure for extracting charge from the second gate; and
a counteracting circuit to prevent extracting charge from the first and second gates beyond a threshold, such that neither the first transistor nor the second transistor is turned completely off.
2. The circuit of claim 1 , wherein the counteracting circuit is adapted to add charge to the first and second gates.
3. The circuit of claim 1 , wherein the counteracting circuit is coupled to drains of the first and second transistors.
4. The circuit of claim 1 , wherein the counteracting circuit includes a current source.
5. The circuit of claim 1 , wherein the counteracting circuit includes:
a cutoff switch, and
a sensor to trigger the cutoff switch when the threshold is reached.
6. The circuit of claim 5 , wherein the cutoff switch is arranged to prevent a high voltage from being applied to the first and second capacitor structures.
7. The circuit of claim 5 , wherein the cutoff switch is arranged to prevent a power supply from being applied to a terminal of the first transistor and to a terminal of the second transistor.
8. The circuit of claim 5 , wherein the cutoff switch is arranged to prevent a power supply from being applied to a well of the first transistor and to a well of the second transistor.