Counteracting overtunneling in nonvolatile memory cells using charge extraction control
View Patent ↗Methods and apparatuses prevent overtunneling in nonvolatile floating gate memory (NVM) cells. An individual cell includes a circuit with a transistor that has a floating gate that stores charge, and a capacitor structure for extracting charge from the gate, such as by tunneling. A counteracting circuit prevents extracting charge from the floating gate beyond a threshold, therefore preventing overtunneling or correcting for it. In one embodiment, the counteracting circuit supplies electrons to the floating gate, to compensate for tunneling beyond a point. In another embodiment, the counteracting circuit includes a switch, and a sensor to trigger the switch when the appropriate threshold is reached. The switch may be arranged in any number of suitable ways, such as to prevent a high voltage from being applied to the capacitor structure, or to prevent a power supply from being applied to a terminal of the transistor or to a well of the transistor.
1. A circuit comprising:
a transistor with a floating gate;
a capacitor structure for extracting charge from the floating gate; and
a counteracting circuit to prevent extracting charge beyond a threshold, said counteracting circuit preventing said transistor from turning off due to an imbalance between charge added to the floating gate and charge extracted from the floating gate.
2. The circuit of claim 1 , wherein the transistor is a pFET injection transistor.
3. The circuit of claim 2 , further comprising:
a coupling capacitor coupled between the floating gate and a source of the injection transistor.
4. The circuit of claim 1 , wherein extracting is performed by tunneling.
5. The circuit of claim 1 , wherein the transistor is an nFET transistor.
6. The circuit of claim 1 , wherein the threshold is a preset amount of electrical current.
7. The circuit of claim 6 , wherein the preset amount of electrical current is associated with a minimum channel current required to maintain a conducting channel in the transistor.
8. The circuit of claim 1 , wherein the threshold is a preset amount of charge.
9. The circuit of claim 1 , wherein the threshold is a preset electrical potential.
10. The circuit of claim 1 , wherein the capacitor structure is made from a MOSFET structure.
11. The circuit of claim 1 , wherein the counteracting circuit is adapted to add charge to the gate.
12. The circuit of claim 1 , wherein the counteracting circuit is coupled to a drain of the transistor.
13. The circuit of claim 1 , wherein the counteracting circuit includes a current source.
14. The circuit of claim 1 , wherein the counteracting circuit includes a transistor having a gate coupled to a reference voltage.
15. The circuit of claim 1 , wherein the counteracting circuit includes:
a current sensor to monitor a drain current of the memory cell and to generate a trigger event when the threshold is reached, and
a pulse driver to add charge to the gate responsive to the trigger event.
16. The circuit of claim 15 , wherein the current sensor includes:
a current sense amplifier, and
a controller to provide a control signal responsive to the trigger event, and
the pulse driver adds charge responsive to the control signal.
17. The circuit of claim 15 , wherein the threshold is a preset amount of electrical current.
18. The circuit of claim 17 , wherein the preset amount of electrical current is associated with a minimum channel current required to maintain a conducting channel in the transistor.
19. The circuit of claim 1 , wherein the counteracting circuit includes a cutoff switch, and
a sensor to trigger the cutoff switch when the threshold is reached.
20. The circuit of claim 19 , wherein the cutoff switch is arranged to prevent a high voltage from being applied to the capacitor structure.
21. The circuit of claim 19 , wherein the cutoff switch is arranged to prevent a power supply from being applied to a terminal of the transistor.
22. The circuit of claim 19 , wherein the cutoff switch is arranged to prevent a power supply from being applied to a well of the transistor.
23. A memory device comprising:
means for extracting charge from a floating gate of a transistor; and
means for counteracting the extraction of charge if an extraction threshold is sensed, said means for counteracting preventing said transistor from turning off due to an imbalance between charge added to the floating gate and charge extracted from the floating gate.
24. The device of claim 23 , wherein the extraction threshold is sensed by sensing a preset current.
25. The device of claim 24 , wherein the preset current is associated with a minimum channel current required to maintain a conducting channel in the transistor.
26. The device of claim 23 , wherein the extraction threshold is sensed by sensing a potential.
27. The device of claim 23 , wherein the counteracting means adds charge to the gate.
28. The device of claim 23 , wherein the extracting means applies a high voltage to a capacitor structure.
29. The device of claim 28 , wherein the counteracting means switches off the high voltage.
30. The device of claim 23 , wherein the counteracting means switches off power to a terminal of the transistor.
31. The device of claim 23 , wherein the counteracting means switches off power to a well of the transistor.
32. A method comprising:
extracting charge from a floating gate of a transistor; and
if an extraction threshold is sensed, counteracting the extraction of charge by preventing said transistor from turning off due to an imbalance between charge added to the floating gate and charge extracted from the floating gate.
33. The method of claim 32 , wherein the extraction threshold is sensed by sensing a preset current.
34. The method of claim 33 , wherein the preset current is associated with a minimum channel current required to maintain a conducting channel in the transistor.
35. The method of claim 32 , wherein the extraction threshold is sensed by sensing a potential.
36. The method of claim 32 , wherein counteracting is performed by adding charge to the gate.
37. The method of claim 32 , wherein the charge is extracted by applying a high voltage to a capacitor structure.
38. The method of claim 37 , wherein counteracting is performed by switching off the high voltage.
39. The method of claim 32 , wherein counteracting is performed by switching off power to a terminal of the transistor.
40. The method of claim 32 , wherein counteracting is performed by switching off power to a well of the transistor.