Multi-port memory utilizing an array of single-port memory cells

1. A random access memory device comprising:

a plurality of memory cells arranged in a two-dimensional array, each memory cell connected to a single word-line and a pair of bit-lines;

read/write logic to receive first and second memory addresses, and a core clock signal, the read/write logic to perform any combination of two read/write operations to the first and second memory addresses during a single cycle of the core clock signal received at the memory device, and the read/write logic to read/write data received at the memory device to the first and second memory locations during different portions of the single cycle of the core clock signal.

2. The random access memory device of claim 1 , wherein the read/write logic, the two-dimensional array and internally generated memory clock control logic are integrated into one logical component.

3. The random access memory device of claim 1 , wherein one read/write operation is performed during a first portion of the core clock signal cycle, and a second read/write operation is performed during a second portion of the core clock signal cycle.

4. The random access memory device of claim 1 , further comprising:

internal memory clock control logic to generate an internal clock signal, the internal clock signal derived from a core clock signal received from a core clock signal generator external to the memory device.

5. The memory device of claim 2 , wherein each interface component accessing the memory device is clocked at the same frequency as the core clock signal.

6. A machine-readable medium storing data and instructions, which when executed by a machine, cause the machine to generate a representation of the random access memory device of claim 1 .

7. The machine-readable medium of claim 6 storing a memory compiler to provide a design for one or more lithographic masks used in fabricating the random access memory device.

8. A method comprising:

receiving, at a dual-port memory device, first and second memory addresses, each memory address corresponding to a row of single-port memory cells coupled to a common word-line in an array of single-port memory cells;

during a first portion of a core clock cycle, reading or writing data from/to the first memory address; and

during a second portion of the core clock cycle, reading or writing data from/to the second memory address.

9. The method of claim 8 , wherein reading data from the first memory address comprises:

decoding the first memory address and asserting a word-line corresponding to a memory location associated with the first memory address during a first portion of the core clock cycle.

10. The method of claim 9 , wherein reading data from the first memory address comprises:

sensing a voltage differential between a pair of bit-lines coupled to each single port memory cell coupled to the asserted word-line; and

for each bit cell coupled to the asserted word-line, latching a logical value in a data latch, the logical value based on the voltage differential sensed between the pair of bit-lines.

11. The method of claim 8 , wherein writing data to the second memory address includes:

pre-charging a pair of bit-lines for each column of memory cells in the array of memory cells; and

decoding the second memory address and asserting a word-line corresponding to a memory location associated with the second memory address during a second portion of the core clock cycle.

12. An apparatus comprising:

a core clock signal generator to generate a core clock signal that cycles high and low at a predetermined frequency;

at least one processor logic to process data; and

a multi-port memory device having an array of single-port memory cells and N number of memory ports for receiving N number of memory address locations, the multi-port memory device capable of performing N number of any combination of read and/or write operations to the array of single port memory cells during a single clock cycle of the core clock signal, wherein the multi-port memory receives the core clock signal from the core clock signal generator, wherein the memory device performs the N number of any combination of read and/or write operations to the array of single port memory cells during a single clock cycle of the core clock signal by performing one operation during each 1/N portion of the core clock cycle.

13. The apparatus of claim 12 , wherein the core clock signal is coupled to both the processor logic and the multi-port memory so that the processor logic and the multi-port memory device operate at the frequency of the core clock signal.

14. The apparatus of claim 12 , wherein each memory address location corresponds to a row of single-port memory cells connected to a common word-line.

15. The apparatus of claim 12 , wherein, during a write operation, a port is to receive a data signal indicating a data value to be written to the memory location in the array of single-port cells corresponding to the memory address received at the port.

16. The apparatus of claim 12 , further comprising:

application specific logic to perform application specific processing of data; and

input/output logic to send and receive data to one or more components external to the apparatus.

17. A machine-readable medium storing data and instructions, which when executed by a machine, cause the machine to generate a representation of the apparatus of claim 12 .

18. The machine-readable medium of claim 17 storing a memory compiler to provide a design for one or more lithographic masks used in fabricating the apparatus.