System and method for improving access efficiency to a dynamic random access memory

1. A memory controller for controlling a dynamic random access memory (DRAM), the memory controller comprising:

a content addressable memory (CAM) based decision control module for determining a next best access request for the DRAM, the CAM based decision control module comprising:

a CAM access storage module for storing a plurality of access requests, the CAM access storage module including:

address bits indicating a complete memory address;

bits indicating if an entry is used or not;

tag bits indicating an order of a requested read operation;

priority bits; and

next table information;

a next access table module for storing the next best access request; and

a decision logic module for determining the next best access request based on results from the CAM access storage module and the next access table module; and

a DRAM access control interface for implementing signaling required to access the DRAM.

2. The memory controller of claim 1 , wherein the CAM based decision control module further comprises a DRAM scheduler for scheduling the plurality of access requests.

3. The memory controller of claim 1 , wherein the next access table module includes:

bits indicating if an entry is to be used;

priority bits including relative importance of an access;

page hit bits indicating if an access is within an open page; and

an index into contents of the CAM access storage module.

4. The memory controller of claim 1 , wherein the decision logic module determining the next best access request by implementing an algorithm.

5. The memory controller of claim 1 , further comprising an interface for connecting the DRAM access control interface with memory.

6. The memory controller of claim 5 , wherein the DRAM access control interface creates signals and timing to control read and write process with the memory.

7. A method of accessing a dynamic random access memory (DRAM), the method comprising:

storing a plurality of access requests in a content addressable memory access storage module, the CAM access storage module including:

address bits indicating a complete memory address;

bits indicating if an entry is used or not;

tag bits indicating an order of a requested read operation;

priority bits; and

next table information;

determining which of the stored access requests is a next best access request based on results from the CAM access storage module and the next access table module; and

processing the next best access request.

8. The method of claim 7 , wherein the determining comprises at least one of:

determining an access request to an open page of a DRAM bank; and

determining the access request to the DRAM bank.

9. The method of claim 7 , wherein the determining comprises:

holding the next best access request for a period of time.

10. The method of claim 7 further comprising:

maintaining order of the plurality of access requests for the processing.

11. The method of claim 7 further comprising:

detecting data collisions of the plurality of access requests for the processing.

12. The method of claim 11 further comprising:

managing the data collisions of the plurality of access requests.

13. A method of operating a memory controller to control a dynamic random access memory (DRAM), the method comprising:

determining a next best access request for the DRAM, wherein the next best access request is determined by a content addressable memory (CAM) based decision control module comprised in the memory controller

storing a plurality of access requests, wherein the plurality of access requests are stored by a CAM access storage module comprised in the memory controller, the storing a plurality of access requests including storing access requests in a form comprising:

bits indicating if an entry is used or not;

address bits indicating a complete memory address;

tag bits indicating an order of a requested read operation;

priority bits; and

next table information;

storing the next best access request, wherein the next best access request is stored by a next access table module comprised in the memory controller;

determining the next best access request, by a decision logic module comprised in the memory controller, based on results from the CAM access storage module and the next access table module; and

implementing signaling required to access the DRAM, wherein the signaling is implemented by a DRAM scheduler comprised in the memory controller.

14. The method of claim 13 further comprising:

scheduling the plurality of access requests, wherein the plurality of access requests are scheduled by a DRAM scheduler comprised in the memory controller.

15. The method of claim 13 , wherein the CAM access storage module further comprises:

bits indicating if an entry is used or not;

address bits indicating a complete memory address;

tag bits indicating an order of a requested read operation;

priority bits; and

next table information.

16. The method of claim 13 , wherein the next access table module comprises:

bits indicating if an entry is too be used;

priority bits including relative importance of an access;

page hit bits indicating if an access is within an open page; and\

an index into contents of the CAM access storage module; and

the storing the next best access request includes storing the next best access request in a form comprising:

bits indicating if an entry is to be used;

priority bits including relative importance of an access;

page hit bits indicating if an access is within an open page; and

an index into contents of the CAM access storage module.

17. The method of claim 13 wherein determining the next best access request comprises:

implementing an algorithm.

18. The method of claim 13 , further comprising:

connecting the DRAM access control interface with memory through an interface.

19. The method of claim 13 further comprising:

creating signals and timing to control read and write process with memory, wherein the creating is performed by the DRAM access control interface.