Distributed table-driven power mode computation for controlling optimal clock and voltage switching
View Patent ↗A method for computing the optimal power mode for a system-on-chip (SoC) in which both the clock and Vdd settings are controlled. Information from hardware blocks is synthesized into a global power mode for the entire SoC. The clocks can be disabled or enabled, and Vdd voltages can be disabled, set at a nominal operating level, and set at a retention level in which the state of memory and registers is retained.
1. A method for providing the optimal power mode for a system on chip (SoC), comprising:
dividing the SOC into hardware blocks comprising power loads having no more than one clock, one Vdd, and one embedded Vdd switch;
storing a respective power state of each of the power loads in a transition table, wherein the transition table comprises a plurality of rows and columns, wherein a row denotes the power state and the columns denote power management resources comprising clocks, Vdds and embedded Vdd switches; and
selecting a row from the transition table with a predetermined maximum benefit and affordable latency as an optimal power mode, wherein maximum benefit is defined as a largest amount of a predetermined criterion from among all the plurality of rows, and affordable latency is an amount of computer cycles taking to initiate performance of one or more operations in a selected row.
2. The method according to claim 1 , wherein the maximum benefit comprises a largest amount of mWatts saved by selecting a particular row.
3. The method according to claim 1 , further comprising:
executing a mode transition based on the selected row.
4. The method according to claim 1 , wherein for each power load the following information is stored:
a clock id;
a Vdd id;
two benefit values for Standby state, and PowerDown state, respectively;
a Powerdown latency value; and
a Wakeup latency value.
5. The method according to claim 4 , wherein the information stored for each power load further comprises a Retention state.
6. The method according to claim 4 , wherein the transition table is initialized, and the load is in the Active state.
7. The method according to claim 4 , wherein the selecting of a row includes requiring that a sum of the powerdown latency and wakeup latency not exceed a predetermined threshold.
8. The method according to claim 1 , comprising more than one transition table, and wherein the selecting a row from the transition table with a predetermined maximum benefit comprises joining a first row from one transition table with a second row from another transition table thereby causing property values of the joining of the first and second rows to be a sum of individual properties of the first and second rows.
9. The method according to claim 8 , wherein the predetermined threshold of the affordable latency comprises 10% of estimated idle time.
10. A computer program product for use in conjunction with a computer system, the computer program product comprising a tangible computer readable storage medium and a computer program mechanism embedded therein, the computer program mechanism comprising instructions for
dividing a system on chip (SoC) into hardware blocks comprising power loads having no more than one clock, one Vdd, and one embedded Vdd switch;
storing a respective power state of each of the power loads in a transition table, wherein the transition table comprises a plurality of rows and columns, wherein a row denotes the power state and the columns denote power management resources comprising clocks, Vdds and embedded Vdd switches; and
selecting a row from the transition table with maximum benefit and affordable latency as an optimal power mode, wherein maximum benefit is defined as a largest amount of a predetermined criterion from among all the plurality of rows, and wherein affordable latency is defined as an amount of computer cycles required to initiate performance of one or more operations in a selected row.
11. The computer program product according to claim 10 , further comprising for each power load, instructions for storing:
a clock id;
a Vdd id;
two benefit values, which respectively indicate how beneficial a transition to the power state/mode represented by the row, for a Standby state and a PowerDown state;
a Powerdown latency comprising a number of compute cycles it takes to perform a state save operation; and
a Wakeup latency comprising a number of compute cycles it takes to perform a state restore operation.
12. The computer program product according to claim 11 , wherein the storing further comprises storing a Retention state.
13. The computer program product according to claim 12 , wherein the transition table is initialized, and the load is in the Active state.
14. The computer program product according to claim 11 , comprising more than one transition table, and wherein the selecting a row from the transition table comprises joining a first row from a first transition table with a second row from another transition table thereby causing property values of the joining of the first and second rows to be a sum of individual properties of the first and second rows.
15. The computer program product according to claim 11 , wherein the SoC comprises multiple CPU cores.
16. The computer program product according to claim 11 , wherein the power loads are arranged in a tree hierarchy in the transition table.
17. The computer program product according to claim 11 , wherein the maximum benefit comprises a largest amount of mWatts saved by selecting a particular row.