IP Library Granted Patent US 7,177,182
Granted Patent B2
US 7,177,182 · App. 10/814,868 · Granted Feb 13, 2007

Rewriteable electronic fuses

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Quick Facts
Patent No.
US 7,177,182
App. No.
10/814,868
Granted
Feb 13, 2007
Kind
B2
Abstract

Rewriteable electronic fuses include latches and/or logic gates coupled to one or more nonvolatile memory elements. The nonvolatile memory elements are configured to be programmed to memory values capable of causing associated electronic circuits to settle to predetermined states as power-up or reset signals are applied to the fuses. Although not required, the nonvolatile memory elements used in the rewriteable electronic fuses may comprise floating-gate transistors. An amount of charge stored on the floating gate of a given floating-gate transistor determines the memory value and, consequently, the state to which a fuse settles upon power-up or reset of the fuse.

Claims (28)

1. A reprogrammable fuse apparatus, comprising:

a plurality of rewriteable electronic fuses, each having a nonvolatile memory element, arrayed in a predetermined configuration; and

a plurality of high-voltage switches, each high-voltage switch corresponding to an associated electronic fuse of said plurality of electronic fuses, and each high-voltage switch having a high-voltage input terminal and a fuse-state state-setting input terminal,

wherein a given electronic fuse of the plurality of electronic fuses is programmed by selecting and coupling an associated control signal to the given electronic fuse.

2. The reprogrammable fuse apparatus of claim 1 , wherein each electronic fuse comprises a CMOS latch having two cross-coupled inverters.

3. The reprogrammable fuse apparatus of claim 1 , wherein the nonvolatile memory element of each electronic fuse comprises a floating-gate transistor having a floating gate, an amount of charge on the floating gate of any given nonvolatile memory element determining a memory value of the given nonvolatile memory element.

4. The reprogrammable fuse apparatus of claim 3 , wherein each nonvolatile memory element includes a first capacitor, each first capacitor of any given nonvolatile memory element having a first plate in common with the floating gate of the floating-gate transistor of the given nonvolatile memory element.

5. The reprogrammable fuse apparatus of claim 1 , wherein the nonvolatile memory elements are manufactured in a standard CMOS fabrication process.

6. The reprogrammable fuse apparatus of claim 3 , wherein each floating-gate transistor of each electronic fuse is a transistor selected from the group consisting of: nFET, pFET, FinFET, and multi-gate FET.

7. The reprogrammable fuse apparatus of claim 1 , wherein said nonvolatile memory element of each electronic fuse is a memory element using a mechanism selected from the group consisting of magnetoresistive , ferroelectric, phase-change, and dielectric, for nonvolatile storage of information.

8. The reprogrammable fuse apparatus of claim 3 , wherein the amount of charge on a floating gate may be changed using Fowler-Nordheim tunneling.

9. The reprogrammable fuse apparatus of claim 3 , wherein the amount of charge on a floating gate may be changed using hot-electron injection.

10. The reprogrammable fuse apparatus of claim 3 , wherein the amount of charge on a floating gate may be changed using direct tunneling.

11. The reprogrammable fuse apparatus of claim 3 , wherein the amount of charge on a floating gate may be changed using hot-hole injection.

12. The reprogrammable fuse apparatus of claim 3 , wherein the amount of charge on a floating gate may be changed using ultraviolet radiation exposure.

13. The reprogrammable fuse apparatus of claim 4 , wherein each nonvolatile memory element further includes a second capacitor, each second capacitor of any given nonvolatile memory element having a first plate in common with the floating gate of the floating-gate transistor of the given nonvolatile memory element.

14. The reprogrammable fuse apparatus of claim 2 , wherein each electronic fuse has a capacitive element coupled to an output of its latch.

15. The reprogrammable fuse apparatus of claim 13 , wherein a second plate of the first capacitor in each electronic fuse is coupled to a first output of an associated high-voltage switch and a second plate of the second capacitor in each electronic fuse is coupled to a second output of the associated high-voltage switch.

16. A reprogrammable electronic fuse apparatus, comprising:

a plurality of rewriteable electronic fuses arrayed in a predetermined configuration; and

a plurality of high-voltage switches, each high-voltage switch corresponding to an associated electronic fuse of said plurality of electronic fuses, and each high-voltage switch having a high-voltage input terminal and at least one fuse-state state-setting input terminal,

wherein a given electronic fuse of the plurality of electronic fuses is programmed by selecting and coupling an associated control signal to the given electronic fuse.

17. A reprogrammable fuse element for providing one of two fuse states, comprising:

logic set and reset inputs configured to respectively set the fuse to a first state and reset the fuse to a second state;

voltage inputs for ground, Vdd, intermediate-voltage and high-voltage; and

at least one output indicating said one of two fuse states.

18. The programmable fuse element of claim 17 , further comprising an initialize input for initializing the fuse element.

19. The programmable fuse element of claim 17 , wherein a magnitude of a signal on the at least one output is as large as a magnitude of the high-voltage voltage input and a magnitude of a signal on the set and reset inputs is less than the magnitude of the high-voltage voltage input.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 8, 2010
From: VIRAGE LOGIC CORPORATION; VL C.V.; ARC CORES LIMITED; ARC INTERNATIONAL I.P., INC.; ARC INTERNATIONAL INTELLECTUAL PROPERTY, INC.; ARC INTERNATIONAL LIMITED, FORMERLY ARC INTERNATIONAL PLC; ARC INTERNATIONAL (UK) LIMITED
To: SYNOPSYS, INC.
Reel/Frame 025105/0907 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 6, 2008
From: IMPINJ, INC.
To: VIRAGE LOGIC CORPORATION
Reel/Frame 021637/0351 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 1, 2004
From: DIORIO, CHRISTOPHER J.; BERNARD, FREDERIC J.; HUMES, TODD E.; PESAVENTO, ALBERTA
To: IMPINJ, INC.
Reel/Frame 015210/0476 →