Methods and apparatuses for a ROM memory array having twisted source or bit lines

1. An apparatus, comprising:

a read only memory arrayed in a plurality of rows and columns;

a first column of memory cells organized into groups of memory cells including a first group of memory cells and a second group of memory cells;

a first source line connected to one or more memory cells in the first group of memory cells, the first source line to change its voltage state during a read operation on one or more bit cells in the first group; and

a second source line connected to one or more memory cells in the second group of memory cells, the second source line to maintain its voltage state during the read operation.

2. The apparatus of claim 1 , further comprising:

a first twisted cell in between a last bit cell in the first group of memory cells and a beginning bit cell in the second group of memory cells.

3. The apparatus of claim 1 , further comprising:

a first twisted cell to break a geometry of the read only memory to create subsections within the first column of memory cells.

4. The apparatus of claim 1 , wherein the first source line has a twisted geometry.

5. The apparatus of claim 1 , further comprising:

a first address decoder circuitry operable to generate a signal to change the voltage state of the first source line during the read operation.

6. The apparatus of claim 1 , further comprising:

a first bit line connected to one or more memory cells in the first group and one or more memory cells in the second group.

7. The apparatus of claim 1 , wherein the first source line lies orthogonal to the first memory column.

8. A read only memory array, comprising:

a plurality of bit cells organized into groups of bit cells;

one or more bit cells in a first group of bit cells connect to a first source line and a first bit line;

one or more bit cells in a second group of bit cells connect to the first source line and a second bit line;

one or more bit cells in a third group of bit cells connect to the first source line and a third bit line; and

a first twisted cell to break the geometry of the read only memory array to create groups of bit cells within a first column of bit cells.

9. The read only memory array of claim 8 , further comprising:

a virtual ground circuit to change the first source line from a same voltage state as the first bit line to a different voltage state than the voltage state of the first bit line when a read operation is initiated on a first bit cell in the first group of cells.

10. A method, comprising:

performing a read operation on a first bit cell in a column of bit cells, wherein all of the bit cells in the column of bit cells share a common bit line; and

preserving stored charge in a first group of bit cells in the column of bit cells during the read operation by pairing the first bit cell to a first source line and the first group of bit cells to a second source line.

11. The method of claim 10 , further comprising:

changing a first voltage state of the first source line during the read operation while maintaining a second voltage state of the second source line during the read operation.

12. An apparatus, comprising:

means for performing a read operation on a first bit cell programmed as a logical one in a column of bit cells, wherein all of the bit cells in the column of bit cells share a common precharged bit line; and

means for preserving stored charge in the precharged bit line during the read operation on the first bit cell by pairing the first bit cell to a first source line and the first group of bit cells to a second source line.

13. The apparatus of claim 12 , further comprising:

means for changing a first voltage state of the first source line during the read operation while maintaining a second voltage state of the second source line during the read operation.

14. The apparatus of claim 12 , wherein the first source line has a twisted geometry.

15. A machine readable medium that stores data representing an integrated circuit, comprising:

a read only memory arrayed in a plurality of rows and columns;

a first column of memory cells organized into groups of memory cells including a first group of memory cells and a second group of memory cells;

a first source line connected to one or more memory cells in the first group of memory cells, the first source line to change its voltage state during a read operation on one or more bit cells in the first group; and

a second source line connected to one or more memory cells in the second group of memory cells, the second source line to maintain its voltage state during the read operation.

16. The machine readable medium of claim 15 , wherein the machine readable medium comprises a memory compiler to provide a layout utilized to generate one or more lithographic masks used in the fabrication of the read only memory.

17. The machine readable medium of claim 16 , wherein the integrated circuit further comprises:

a first twisted cell in between a last bit cell in the first group of memory cells and a beginning bit cell in the second group of memory cells.

18. The machine readable medium of claim 16 , wherein the first source line has a twisted geometry.

19. The machine readable medium of claim 18 , wherein the integrated circuit further comprises:

a first twisted cell to route the first source line over at least two memory columns prior to aligning the first source line to run parallel to that memory column.

20. The machine readable medium of claim 16 , wherein the integrated circuit further comprises:

a first bit line connected to one or more memory cells in the first group and one or more memory cells in the second group.