IP Library Granted Patent US 8,063,623
Granted Patent B2
US 8,063,623 · App. 12/299,305 · Granted Nov 22, 2011

Analog compensation circuit

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Quick Facts
Patent No.
US 8,063,623
App. No.
12/299,305
Granted
Nov 22, 2011
Kind
B2
Abstract

The present disclosure relates to a compensation circuit for providing compensation over PVT variations within an integrated circuit. Using a low voltage reference current source, the compensation circuit generates directly, from an on-chip reference low voltage supply (V DD ), a reference current (I ref ) that is constant over PVT variations, whereas a detection current (I z ) that is variable over PVT variations is generated by a sensing circuit, which is based on a current conveyor, from a low voltage supply (V DDE −V DD ) applied across a single diode-connected transistor (M 10 ) corresponding to a voltage difference between two reference low voltage supplies. Both currents (I ref , I z ) are then compared inside a current mode analog-to-digital converter that outputs a plurality of digital bits. These digital bits can be subsequently used to compensate for PVT variations in an I/O buffer circuit.

Claims (43)

1. A compensation circuit for providing compensation for one of process, voltage and temperature (PVT) variations within an integrated circuit, said compensation circuit comprising at least:

a reference circuit for generating a reference current that is constant over PVT variations, said reference circuit being configured to directly generate said reference current from a first voltage supply, which is internal to said integrated circuit and configured to provide a low voltage supply, wherein the generation of the reference current is based on a sum of a current having a positive temperature coefficient and another current having a negative temperature coefficient in order to compensate temperature change; and

a sensing circuit, which comprises an output terminal and which is configured to provide at said output terminal a detection current (I z ) that is variable over PVT variations, and to sense said PVT variations through said detection current.

2. A compensation circuit according to claim 1 , wherein said reference circuit comprises:

a proportional-to-absolute-temperature (PTAT) circuit, which comprises a first diode element and a series arrangement of a second diode element and a second resistor, said first diode element and said series arrangement being configured to allow said PTAT circuit to exhibit a positive temperature coefficient (PTC) through a voltage difference across said second resistor between a voltage across said first diode element and a voltage across said series arrangement;

first and third resistive elements, which are respectively connected in parallel with said first diode element and said series arrangement, said first and third resistive elements being respectively passed through by a first current and a third current both exhibiting a negative temperature coefficient (NTC) by being proportional to said voltage across said first diode element;

a current mirror, which comprises a drive input and at least first, second, and third current sources being supplied by said first voltage supply and having first, second, and third transistors respectively, said current mirror being configured to replicate a fifth current that passes through said first transistor into a sixth current that passes through said second transistor, and said sixth current into said reference current that passes through said third transistor, said fifth current and sixth current being constant over PVT variations; and

an operational amplifier, which comprises at least a non-inverting input terminal and an inverting input terminal, said operational amplifier being connected to said current mirror and said PTAT circuit such that said non-inverting input terminal has a same voltage level as said voltage across said first diode element and said inverting input terminal has a same voltage level as that of said series arrangement, and configured to drive said current mirror through said drive input.

3. A compensation circuit according to claim 1 , wherein said sensing circuit comprises:

a current conveyor for conveying a current from an input terminal towards said output terminal, said current conveyor further comprising a reference terminal, which is connected to a reference voltage supply; and

a diode-connected transistor for generating a low positive voltage drop across it, said diode-connected transistor being connected between a second voltage supply and said input terminal.

4. A compensation circuit according to claim 3 , wherein said voltage drop is equal to a voltage difference between said second voltage supply and said reference voltage supply.

5. A compensation circuit according to claim 3 , wherein said compensation circuit further comprises: an analog-to-digital converter, which is configured to provide at its output a plurality of digital bits based on a comparison between said reference current and said detection current.

6. A compensation circuit according to claim 5 , wherein said compensation circuit further comprises: a buffer circuit, which is configured to receive at its input said plurality of digital bits.

7. A compensation circuit according to claim 1 , wherein said first voltage supply is a digital core voltage supply.

8. A compensation circuit according to claim 4 , wherein said reference voltage supply is said first voltage supply.

9. A compensation circuit according to claim 2 , wherein said second diode element is a set of N parallel-connected diode elements, wherein N is an integer greater than unity.

10. A compensation circuit according to claim 2 , wherein said fifth current is split into said first current and a fourth current that flows through said first diode element, and said sixth current is split into said third current and a second current that flows through said series arrangement.

11. A compensation circuit according to claim 2 , wherein each one of said first and second diode elements is a diode-connected transistor.

12. A compensation circuit according to claim 3 , wherein said current conveyor is a first generation current conveyor.

13. A method for providing compensation for at least one of process, voltage and temperature (PVT) variations within an integrated circuit, said method comprising at least the steps of:

generating a reference current which is constant over PVT variations, said reference current being generated directly from a first voltage supply, which is internal to said integrated circuit and configured to provide a low voltage supply, wherein the generation of the reference current is based on a sum of a current having a positive temperature coefficient and another current having a negative temperature coefficient in order to compensate temperature change; and

sensing PVT variations through a detection current which is variable over PVT variations, said detection current being provided by said sensing circuit.

14. A method according to claim 13 , wherein said method further comprises the steps of:

comparing said reference current and said detection current; and

outputting a plurality of digital bits towards a buffer circuit for PVT compensation.

15. A method according to claim 13 , wherein said sensing step comprises the steps of:

conveying a current from an input terminal at low impedance level towards an output terminal at high impedance level, said input terminal being at a voltage level equal to that of a reference voltage supply; and

generating a low positive voltage drop across a diode-connected transistor, said diode-connected transistor being connected between a second voltage supply and said input terminal.

16. A compensation circuit for providing compensation for one of process, voltage and temperature (PVT) variations within an integrated circuit, said compensation circuit comprising

a reference circuit means for generating a reference current that is constant over PVT variations, said reference circuit means being configured to directly generate said reference current from a first voltage supply, which is internal to said integrated circuit and configured to provide a low voltage supply, wherein the generation of the reference current is based on a sum of a current having a positive temperature coefficient and another current having a negative temperature coefficient in order to compensate temperature change; and

sensing circuit means comprising an output terminal, for providing at said output terminal a detection current (I z ) that is variable over PVT variations, and for sensing said PVT variations through said detection current.

17. A compensation circuit according to claim 16 , wherein said reference circuit means comprises:

a proportional-to-absolute-temperature (PTAT) circuit, which comprises

a first diode element and a series arrangement of a second diode element and a second resistor, said first diode element and said series arrangement being configured to allow said PTAT circuit to exhibit a positive temperature coefficient (PTC) through a voltage difference across said second resistor between a voltage across said first diode element and a voltage across said series arrangement;

first and third resistive elements, which are respectively connected in parallel with said first diode element and said series arrangement, said first and third resistive elements being respectively passed through by a first current and a third current both exhibiting a negative temperature coefficient (NTC) by being proportional to said voltage across said first diode element;

a current mirror, which comprises a drive input and at least first, second, and third current sources being supplied by said first voltage supply and having first, second, and third transistors respectively, said current mirror being configured to replicate a fifth current that passes through said first transistor into a sixth current that passes through said second transistor, and said sixth current into said reference current that passes through said third transistor, said fifth current and sixth current being constant over PVT variations; and

an operational amplifier, which comprises at least a non-inverting input terminal and an inverting input terminal, said operational amplifier being connected to said current mirror and said PTAT circuit such that said non-inverting input terminal has a same voltage level as said voltage across said first diode element and said inverting input terminal has a same voltage level as that of said series arrangement, and configured to drive said current mirror through said drive input.

18. A compensation circuit according to claim 16 , wherein said sensing circuit means comprises:

a current conveyor for conveying a current from an input terminal towards said output terminal, said current conveyor further comprising a reference terminal, which is connected to a reference voltage supply; and

a diode-connected transistor for generating a low positive voltage drop across it, said diode-connected transistor being connected between a second voltage supply and said input terminal.

19. A compensation circuit according to claim 18 , wherein said voltage drop is equal to a voltage difference between said second voltage supply and said reference voltage supply.

20. A compensation circuit according to claim 18 , wherein said compensation circuit further comprises: an analog-to-digital converter means, which is configured to provide at its output a plurality of digital bits based on a comparison between said reference current and said detection current.

Assignments (32)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
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From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
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CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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