Various methods and apparatuses to route multiple power rails to a cell
View Patent ↗Various methods and apparatuses are described in which an integrated circuit is organized into rows and columns of macro cells having a layout architecture that includes at least two metal layers and a plurality of traces carrying three or more different potentials of voltage routed by the metal layers. A first, a second, and a third adjacent metal layers extend across the integrated circuit. The plurality of traces carry three or more different potentials of voltage and are routed in the metal layers. A first power trace supplies a VDD voltage potential. A second power trace supplies a VSS voltage potential. A third power trace supplies a third voltage potential to support sleep modes and retain data during sleep modes. All three power supply traces connect to one or more transistors in a first macro cell.
1. A method of designing an integrated circuit comprising:
routing, at a computing device, a first power trace in a second metal layer located above a first metal layer,
routing a first power trace in a second metal layer located above a first metal layer, the first power trace carrying a first voltage potential to a row of cells in the integrated circuit, the first voltage potential turned on or off during operation of the integrated circuit;
routing a second power trace in the second metal layer for carrying a second voltage potential to the row of cells in the integrated circuit, the second voltage potential remaining turned on during the operation of the integrated circuit; and
routing a third power trace in the second metal layer for providing a ground potential to the row of cells during the operation of the integrated circuit.
2. The method of claim 1 ,
wherein the second metal layer is routed in a horizontal direction.
3. The method of claim 1 , further comprising:
routing at least one signal trace in a third metal layer above the second metal layer, the third metal layer orientated orthogonal to the second metal layer.
4. The method of claim 1 , further comprising:
routing the first power trace along a first edge of a cell boundary of the first macro cell to share the first power trace with a cell in an adjacent row of cells;
routing the third power trace along a second edge of the cell boundary opposite to the first edge to share the third power trace with another cell in another adjacent row of cells; and
routing the second power trace along an interior of the cell between the first and second edges of the cell boundary.
5. The method of claim 1 , further comprising:
connecting the second power trace to one or more well substrates.
6. An apparatus generated through a method comprising:
routing a first power trace in a second metal layer located above a first metal layer, the first power trace carrying a first voltage potential to a row of cells in an integrated circuit, the first voltage potential turned on or off during operation of the integrated circuit;
routing a second power trace in the second metal layer for carrying a second voltage potential to the row of cells in the integrated circuit, the second voltage potential remaining turned on during the operation of the integrated circuit; and
routing a third power trace in the second metal layer for providing a ground potential to the row of cells during the operation of the integrated circuit.
7. A non-transitory machine-readable medium that stores instructions, which when executed by a machine, to cause the machine to perform operations comprising:
routing a first power trace in a first metal layer to each cell in a row of cells of an integrated circuit, the first power trace carrying a first voltage potential that is turned on or off during operation of the integrated circuit;
routing a second power trace in a second metal layer located above the first metal layer to each cell in the row of cells, the second power trace carrying a second voltage potential that remains turned on during the operation of the integrated circuit; and
routing a third power trace in the second metal layer carrying a ground voltage potential to each cell in the row of cells during the operation of the integrated circuit.
8. The machine-readable medium that stores instructions of claim 7 , wherein the third metal layer is orientated orthogonal to the second metal layer.
9. The machine-readable medium that stores instructions of claim 7 , which executes further instructions to cause the machine to perform the further operations comprising:
routing the second power trace along a first edge of a cell boundary of the first macro cell to share the second power trace with a cell in an adjacent row of cells;
routing the third power trace along a second edge of the cell boundary opposite to the first edge to share the third power trace with another cell in another adjacent row of cells;
routing the first power trace along an interior of the cell between the first and second edges of the cell boundary; and
routing a fourth power trace to connect to one or more well substrates associated with the row of cells.
10. The machine-readable medium of claim 7 , wherein the machine-readable medium further comprises instructions to provide a layout utilized to generate one or more lithographic masks used in the fabrication of the integrated circuit.
11. An apparatus generated through the operations caused by a non transitory machine-readable medium that stores instructions to:
route a first power trace in a first metal layer to each cell in a row of cells of an integrated circuit, the first power trace carrying a first voltage potential that is turned on or off during operation of the integrated circuit;
route a second power trace in a second metal layer located above the first metal layer to each cell in the row of cells, the second power trace carrying a second voltage potential that remains turned on during the operation of the integrated circuit; and
route a third power trace in the second metal layer carrying a ground voltage potential to each cell in the row of cells during the operation of the integrated circuit.
12. The apparatus of claim 11 , wherein the third metal layer is orientated orthogonal to the second metal layer.
13. The apparatus of claim 11 , wherein the machine-readable medium further stores instructions to:
route the second power trace along a first edge of a cell boundary of the first macro cell to share the second power trace with a cell in an adjacent row of cells;
route the third power trace along a second edge of the cell boundary opposite to the first edge to share the third power trace with another cell in another adjacent row of cells;
route the first power trace along an interior of the cell between the first and second edges of the cell boundary; and
route a fourth power trace to connect to one or more well substrates associated with the row of cells.
14. The apparatus of claim 13 , wherein the machine-readable medium further stores instructions to provide a layout utilized to generate one or more lithographic masks used in the fabrication of the integrated circuit.
15. A method of designing an integrated circuit, comprising:
at a computing device, routing a first power trace in a first metal layer to a row of cells in the integrated circuit, the first power trace carrying a first voltage potential that is turned on or off during operation of the integrated circuit;
routing a second power trace in a second metal layer located above the first metal layer to the row of cells, the second power trace carrying a second voltage potential during the operation of the integrated circuit; and
routing a third power trace in the second metal layer carrying a ground voltage potential during the operation of the integrated circuit.
16. The method of claim 15 , further comprising:
routing the second power trace along a first edge of a cell boundary of the first macro cell to share the second power trace with a cell in an adjacent row of cells;
routing the third power trace along a second edge of the cell boundary opposite to the first edge to share the third power trace with another cell in another adjacent row of cells;
routing the first power trace along an interior of the cell between the first and second edges of the cell boundary; and
routing a fourth power trace to connect to one or more well substrates associated with the row of cells.
17. The method of claim 15 , wherein the third metal layer is orientated orthogonal to the second metal layer.
18. An apparatus generated through a method comprising:
routing a first power trace in a first metal layer to a row of cells in an integrated circuit, the first power trace carrying a first voltage potential that is turned on or off during operation of the integrated circuit;
routing a second power trace in a second metal layer located above the first metal layer to the row of cells, the second power trace carrying a second voltage potential during the operation of the integrated circuit; and
routing a third power trace in the second metal layer carrying a ground voltage potential during the operation of the integrated circuit.
19. The apparatus of claim 18 , wherein the third metal layer is orientated orthogonal to the second metal layer.
20. The apparatus of claim 18 , wherein the method further comprises:
routing the second power trace along a first edge of a cell boundary of the first macro cell to share the second power trace with a cell in an adjacent row of cells;
routing the third power trace along a second edge of the cell boundary opposite to the first edge to share the third power trace with another cell in another adjacent row of cells;
routing the first power trace along an interior of the cell between the first and second edges of the cell boundary; and
routing a fourth power trace to connect to one or more well substrates associated with the row of cells.