Non-volatile memory cell with BTBT programming
View Patent ↗A Non-Volatile Memory (NVM) cell and programming method in which the cell can denote at least two logic levels (e.g., 0 and 1) and includes a read-transistor with a floating gate and a Band-To-Band-Tunneling device (BTBT device) sharing the floating gate with the read-transistor. The BTBT device is configured as an injection device for injecting a first charge onto the floating gate when the BTBT device is biased so that it is in accumulation, to set at least one of the logic levels.
1. A Non-Volatile Memory (NVM) cell, comprising:
a floating gate configured to store charge;
at least a first Band-To-Band-Tunneling (BTBT) device coupled to the floating gate and having a first node and a second node;
a read-transistor coupled to the floating gate and having a first node and a second node, the first node of the read transistor and the first node of the BTBT device coupled together;
a read select switch coupled between the second node of the read-transistor and a bit line node; and
a BTBT select switch coupled between the second node of the BTBT device and the bit line node.
2. The NVM cell of claim 1 , further comprising:
a tunneling device coupled between a tunneling line and the floating gate and configured to selectively utilize the mechanism of Fowler-Nordheim tunneling to remove electrons from the floating gate.
3. The NVM cell of claim 1 , wherein:
the at least a first BTBT device is formed in a first region of semiconductor material having a first conductivity type; and
the read-transistor is formed in a second region of semiconductor material having the first conductivity type.
4. The NVM cell of claim 3 , further comprising:
a first dielectric of a first thickness disposed between the floating gate and the first region of semiconductor material; and
a second dielectric of a second thickness disposed between the floating gate and the second region of semiconductor material.
5. The NVM cell of claim 4 , wherein:
the first thickness is greater than the second thickness.
6. A complementary metal oxide semiconductor (CMOS) wafer comprising:
a first device having
a first polarity type,
a first dielectric thickness,
a first source/drain extension profile, and
a first halo profile;
a second device having
the first polarity type,
a second dielectric thickness thicker than the first dielectric thickness, and
a first LDD profile; and
a third device having
the first polarity type,
the second dielectric thickness,
the first source/drain extension profile, and
the first halo profile.
7. The wafer of claim 6 , wherein both the second and third devices are coupled to a first floating gate of a non-volatile memory circuit.
8. The wafer of claim 7 , wherein the third device is configured so that during a read operation its channel current limited to less than one-quarter of the channel current of the first and second devices.
9. The wafer of claim 6 , further comprising:
a fourth device having
a second polarity type opposite the first polarity type, and
the second dielectric thickness,
wherein both the third and fourth devices are coupled to a first floating gate of a non-volatile memory circuit.
10. The wafer of claim 9 , wherein the third device is configured so that during a read operation its channel current limited to less than one-quarter of the channel current of the fourth device.
11. The wafer of claim 6 , wherein the third device further comprises a floating gate formed of a material at least a portion of which has a different doping polarity from the second device.
12. The wafer of claim 6 , wherein the third device is part of a floating gate non-volatile memory cell and the third device is configured so that its source and drain are shorted together.
13. The wafer of claim 6 , wherein the third device is part of a floating gate non-volatile memory cell and the third device is configured so that its source is floating.
14. The wafer of claim 6 , wherein the third device is part of a floating gate non-volatile memory cell and the third device is configured to have a drain and no source.
15. A non-volatile memory (NVM) cell formed on a complementary metal oxide semiconductor (CMOS) wafer comprising, the NVM cell comprising:
a floating gate;
a first device having
a first polarity type,
a first dielectric disposed between the wafer and the floating gate and having a first thickness,
a first source/drain extension profile, and
a first halo profile;
a second device having
the first polarity type,
a second dielectric disposed between the wafer and the floating gate and having a second thickness thicker than the first dielectric thickness, and
a first LDD profile; and
a third device having
the first polarity type,
a third dielectric disposed between the wafer and the floating gate and having the thickness of the second dielectric,
the first source/drain extension profile, and
the first halo profile.
16. A non-volatile memory (NVM) cell, comprising:
a first floating gate transistor of a first conductivity type disposed on a semiconductor substrate, the first floating gate transistor having a first and a second source/drain region disposed within the substrate, each of the first and second source/drain regions having a first dopant concentration, a first floating gate electrode, and a first floating gate dielectric disposed between the first floating gate electrode and the substrate, the first floating gate dielectric having a first thickness;
a second floating gate transistor of the first conductivity type disposed on the semiconductor substrate, the second floating gate transistor having a first and a second source/drain region disposed within the substrate, each of the first and second source/drain regions having a second dopant concentration, a second floating gate electrode electrically coupled to the first floating gate electrode, and a second floating gate dielectric disposed between the second floating gate electrode and the substrate, the second floating gate dielectric having a second thickness, the second transistor configured so that when in operation and when selected an injection current caused by band-to-band tunneling (BTBT) predominates in the second floating gate transistor to inject electrons onto the second floating gate electrode; and
a select circuitry disposed on the semiconductor substrate to selectively cause BTBT in the second floating gate transistor.
17. The NVM cell of claim 16 , wherein the first dopant concentration is less than the second dopant concentration.
18. The NVM cell of claim 17 , further comprising:
a first spacer disposed above the substrate and horizontally adjacent to the first floating gate electrode and the first floating gate dielectric;
a second spacer disposed above the substrate and horizontally adjacent to the second floating gate electrode and the second floating gate dielectric; and
wherein a dopant concentration of at least a portion of a region of the semiconductor substrate below the first spacer is less than a dopant concentration of at least a portion of a region of the semiconductor substrate below the second spacer.
19. The NVM cell of claim 16 , wherein the first floating gate transistor does not have a halo implant and the second floating gate transistor has a halo implant.
20. The NVM cell of claim 16 , wherein the first floating gate transistor does not have a source/drain extension implant and the second floating gate transistor has a source/drain extension implant.
21. The NVM cell of claim 16 , wherein the first floating gate transistor does not have a Lightly Doped Drain (LDD) implant and the second floating gate transistor has an LDD implant.
22. The NVM cell of claim 16 , wherein the first floating gate transistor has a Lightly Doped Drain (LDD) implant and the second floating gate transistor has a source/drain extension implant.