Schottky junction diode devices in CMOS
View Patent ↗A Schottky junction diode device having improved performance is fabricated in a conventional CMOS process. A substrate including a material doped to a first conductivity type is formed. A first well is disposed over the substrate. The first well includes a material doped to a second conductivity type opposite that of the first conductivity type. A region of metal-containing material is disposed over the first well to form a Schottky junction at an interface between the region of metal-containing material and the first well. In one embodiment, a first well contact is disposed in a portion of the first well. A second well is disposed over the substrate wherein the second well includes a material doped to the first conductivity type. In one embodiment, the first well and the second well are not in direct contact with one another.
1. A Schottky junction diode device, comprising:
a substrate including a material doped to a first conductivity type;
a first well disposed in said substrate, said first well including a material doped to a second conductivity type opposite that of the first conductivity type;
a region of metal-containing material disposed in the first well to form a Schottky junction at an interface between the region of metal-containing material and the first well;
a first well contact in electrical contact with the first well;
a second well disposed in said substrate, the second well including a material doped to the first conductivity type, the first well and the second well not being in direct contact with one another; and
a region of the substrate disposed between the first well and the second well,
wherein the first well contact is formed in a closed loop shape which surrounds the Schottky junction.
2. The device of claim 1 , further comprising:
a second well contact in electrical contact with the second well.
3. The device of claim 1 , wherein the closed loop shape is a rectangle.
4. The device of claim 1 , wherein the substrate material doped to a first conductivity type is p-doped.
5. The device of claim 1 , wherein the substrate material doped to a first conductivity type is n-doped.
6. The device of claim 4 , wherein the p-doped substrate material comprises silicon.
7. The device of claim 4 , wherein the p-doped substrate material comprises gallium arsenide.
8. The device of claim 1 , wherein the region of metal-containing material comprises one or more of the materials selected from the group consisting of: titanium, titanium silicide, cobalt, cobalt silicide, nickel, nickel silicide, tungsten, tungsten silicide, gold, manganese, hafnium, silver, aluminum, palladium and platinum.
9. A method for manufacturing a Schottky junction diode device comprising:
forming a substrate including a material doped to a first conductivity type;
forming a first well disposed in said substrate, said first well including a material doped to a second conductivity type opposite that of the first conductivity type;
forming a region of metal-containing material disposed in the first well to create a Schottky junction at an interface between the region of metal-containing material and the first well;
forming a first well contact in electrical contact with the first well;
forming a second well disposed in said substrate, the second well including a material doped to the first conductivity type, the first well and the second well not being in direct contact with one another; and
forming a region of the substrate disposed between the first well and the second well,
wherein the first well contact is formed in a closed loop shape which surrounds the Schottky junction.
10. The method of claim 9 , further comprising:
forming a second well contact in electrical contact with the second well.
11. The method of claim 9 , wherein the closed loop shape is a rectangle.
12. The method of claim 9 , wherein the substrate material doped to a first conductivity type is p-doped.
13. The method of claim 9 , wherein the substrate material doped to a first conductivity type is n-doped.
14. The method of claim 12 , wherein the p-doped substrate material comprises silicon.
15. The method of claim 12 , wherein the p-doped substrate material comprises gallium arsenide.
16. The method of claim 9 , wherein the region of metal-containing material comprises one or more of the materials selected from the group consisting of: titanium, titanium silicide, cobalt, cobalt silicide, nickel, nickel silicide, tungsten, tungsten silicide, gold, manganese, hafnium, silver, aluminum, palladium and platinum.