Methods and apparatuses for external test methodology and initialization of input-output circuits

1. A method for testing input output circuits, comprising:

initializing Input-Output (I-O) circuits in a plurality of I-O circuits for performing an external test on the I-O circuits, wherein the plurality of I-O circuits are segmented together into at least a first I-O segment of two or more I-O circuits; and

providing an on-chip analog bus to provide external access for the external test to two or more input-output pins that provide Parametric Test Measurement (PMU) functionality to the first I-O segment through two or more I-O circuits but less than all of the I-O circuits within the first I-O segment, wherein the on-chip analog bus couples via a switchable device to the two or more input-output pins that an external tester can connect to, and the external tester is configured to provide the PMU functionality to the first I-O segment, wherein the remaining I-O circuits within the first I-O segment couple to the external tester through the two or more I-O circuits.

2. The method of claim 1 , wherein initializing the I-O circuits further comprises:

externally initializing a data value stored at an output of a launch register and a capture register of a wrapper associated with each I-O by writing a known data value to a respective input of the launch register and the capture register; and

clocking the launch register and the capture register in each I-O with one or more strobe signals to write the known data values into the launch register and the capture register of each I-O.

3. The method of claim 2 , wherein initializing I-O circuits further comprises:

performing a full shift-in operation with an external tester of an initialization pattern with the known data values into wrapper circuits of one or more I-O circuits of the plurality of I-O circuits.

4. The method of claim 1 , wherein initializing I-O circuits further comprises:

applying known test patterns to the I-O circuits being tested to perform the external test, wherein the test patterns are provided by an external tester.

5. A machine-readable medium that stores instructions, which when executed by a machine causes the machine to run test sequences recited in the method of claim 1 .

6. A machine-readable medium that stores instructions, which when executed by a machine causes the machine to perform the method of claim 1 .

7. An apparatus, comprising:

a plurality of input-output circuits (I-O circuits) formed into one or more I-O segments of two or more I-O circuits, wherein at least two I-O circuits in each segment of the one or more I-O segments directly couple to an external tester;

an on-chip processor to send signals to a wrapper circuit associated with a first I-O circuit from a first I-O segment of the one or more I-O segments during an initializing of the I-O circuits on the first I-O segment to control an operational mode of one or more registers in the wrapper circuit; and

a strobe bus, the on-chip processor to initialize a data value stored at an output of a launch register and a capture register of each I-O by writing a known data value to a respective input of the launch register and the capture register and clocking the launch register and the capture register in each I-O with one or more strobe signals from the strobe bus to write the known data values into the launch register and the capture register of each input-output circuit.

8. A machine-readable medium that stores instructions, which when executed by the machine, to cause the machine to create a device via an Electronic Design Automation process, according to the apparatus of claim 7 .

9. A method for testing input output circuits, comprising:

performing an external leakage current test on Input-Output (I-O) circuits in a plurality of I-O circuits, wherein the plurality of I-O circuits are segmented together into at least a first I-O segment of two or more I-O circuits;

providing an on-chip analog bus to provide external access for the external test to an input-output pin that provides Parametric Test Unit (PMU) functionality to the first I-O segment through at least a first I-O within the first I-O segment, wherein the on-chip analog bus couples via a switchable device to the on-chip analog bus couples via a switchable device to the input-output pin that an external tester can connect to, and the external tester is configured to provide the PMU functionality to the first I-O segment;

measuring I-O leakage current from each I-O through the on-chip analog test bus; and

calibrating the measured leakage current of each I-O under test for the presence of leakage current from the on-chip analog test bus.

10. The method of claim 9 , wherein performing a leakage current external test further comprises:

disabling an output driver of every I-O circuit in the first I-O segment connected to a first pin of the two or more input-output pins, connecting the PMU to a ground voltage potential or power supply DC voltage potential; and

determining total leakage current from the first I-O segment by measuring current flowing from the disabled I-O circuits to the PMU.

11. The method of claim 9 , further comprising:

measuring a first I-O leakage current from the first I-O directly connected to an external tester in the first I-O segment by forcing a voltage and disabling an output driver of each I-O directly connected to the external tester.

12. The method of claim 11 , further comprising:

connecting the first I-O directly connected to the external tester in the first I-O segment to the on-chip analog test bus; and

measuring a second I-O leakage current from the first I-O directly connected to the external tester, wherein the measured second I-O leakage current includes the leakage current from the on-chip analog test bus.

13. The method of claim 12 , further comprising:

determining the on-chip analog bus leakage current by subtracting the first measured leakage current from the measured second I-O leakage current.

14. The method of claim 13 , further comprising:

connecting a third I-O that does not directly connect to the external tester to the on-chip analog bus as well as to the external tester via the first I-O that directly connects to the external tester; and

measuring a third I-O leakage current from the third I-O.

15. The method of claim 14 , further comprising:

determining the I-O leakage current for the third I-O by subtracting out the measured second I-O leakage current for the first I-O directly connected to the external tester in the first I-O segment from the measured third I-O leakage current.

16. The method of claim 11 , wherein performing the leakage test further comprises:

applying test patterns to the I-O circuits being tested to perform the external test with the external tester.

17. A machine-readable medium that stores instructions, which when executed by a machine causes the machine to perform the method of claim 9 .

18. An apparatus, comprising:

a plurality of input-output circuits on a chip, wherein less than all of the plurality of input-output circuits on the chip directly couple to an external tester;

a wrapper circuit that includes one or more registers and is associated with a first input-output circuit from the plurality of input-output circuits;

an on-chip processor to send signals to the wrapper circuit associated with the first input-output circuit from the group of input-output circuits during a leakage current test of the input-output circuits to control an operational mode of one or more registers in the wrapper circuit; and

an on-chip analog test bus, wherein the first input-output circuit to couple to the on-chip analog test bus via one or more switches, the on-chip analog test bus to couple to a second input-output circuit directly coupled to the external tester and the on-chip processor to send signals to the wrapper circuit associated with the first input-output circuit during the leakage current test of the input-output circuits to control whether the one or more switches are open or closed during the leakage current test of the first input-output circuit.

19. The apparatus of claim 18 , wherein the wrapper circuit includes combinational logic coupled to the one or more registers and the on-chip processor to send control signals to the combinational logic coupled to a first update register from the one or more registers and a first switch on the analog test bus from the one or more switches, to allow each individual input-output circuit's output driver circuit to couple to the analog test bus depending on a value of a first test vector supplied to the wrapper circuit, the first test vector supplied by an external tester.

20. The apparatus of claim 19 , wherein the on-chip processor has a mode register to set various modes to control the operational mode of the one or more registers.

21. A method for testing input output circuits, comprising:

performing an external continuity test to determine whether a pad of an Input-Output (I-O) circuit being tested is connected to an external package pin on a chip, the chip comprising a plurality of I-O circuits, wherein the plurality of I-O circuits are segmented together into at least a first I-O segment of two or more I-O circuits; and

providing a first on-chip analog bus to provide external access for the external test to an external tester to the first I-O segment through two or more I-O circuits but less than all of the I-O circuits within the first I-O segment, wherein the first on-chip analog bus couples via a switchable device to the pad that the external tester can connect to.

22. The method of claim 21 , wherein performing the continuity test comprises:

connecting a first I-O in the first segment to an off-chip resistive load.

23. The method of claim 22 , further comprising:

disabling an output driver circuit of the first I-O;

connecting the first I-O to the on-chip analog test bus;

forcing a voltage through a Parametric Measurement Unit (PMU) connected to the first I-O;

measuring current at the output of the first I-O; and

determining that the pad of the first I-O is connected to the external package pin if the measured current at the output is larger than a leakage current of the first I-O.

24. The method of claim 21 , wherein performing the continuity test comprises:

connecting a first I-O in the first segment to an off-chip capacitive load.

25. The method of claim 21 , further comprising:

enabling the output driver circuit of the first I-O;

performing a delay test thru the first I-O to detect an amount of delay time through the first I-O;

determining that the pad of the first I-O is not connected to the external package pin if the detected amount of delay time is smaller than an expected delay, given the off-chip capacitive load.

26. The method of claim 21 , wherein performing the continuity test comprises:

connecting a first I-O in the first segment to a second I-O in the first segment; and

detecting logic written to the first I-O output at the second I-O receiver to determine if pad-to-pin connection is adequate for both the first and the second I-O circuits.

27. The method of claim 21 , wherein performing the continuity test further comprises:

applying test patterns to the I-O circuits being tested to perform the external test, wherein the test patterns are provided by an external tester.

28. A machine-readable medium that stores instructions, which when executed by a machine causes the machine to run test sequences recited in the method of claim 21 .

29. A machine-readable medium that stores instructions, which when executed by a machine causes the machine to perform the method of claim 21 .