Compact virtual ground diffusion programmable ROM array architecture, system and method
View Patent ↗A compact, shared source line and bit line architecture for a diffusion programmable ROM. In one embodiment, a ROM circuit or instance includes a plurality of storage cells organized as an array of rows columns. A shared source line is associated with a first pair of adjacent columns, the shared source line being maintained at a predetermined level, wherein source terminals of storage cells in the adjacent columns are electrically coupled to the shared source line. A shared bit line is associated with a second pair of adjacent columns, the shared bit line being maintained at the predetermined level, wherein drain terminals of storage cells in the adjacent columns are electrically coupled to the shared bit line.
1. A Read-Only Memory (ROM) circuit, comprising:
a plurality of storage cells organized as an array of rows and columns;
a shared source line associated with a first pair of adjacent columns, said shared source line being maintained at a first predetermined level, wherein source terminals of storage cells in said adjacent columns of said first pair are electrically coupled to said shared source line; and
a shared bit line associated with a second pair of adjacent columns, said shared bit line being maintained at a second predetermined level, wherein drain terminals of storage cells in said adjacent columns of said second pair are electrically coupled to said shared bit line.
2. The ROM circuit as set forth in claim 1 , wherein said first predetermined level comprises a voltage level to which said shared source line is precharged.
3. The ROM circuit as set forth in claim 1 , wherein said second predetermined level comprises a voltage level to which said shared bit line is precharged.
4. The ROM circuit as set forth in claim 1 , wherein said shared source line is operable to be driven low upon commencing a memory access operation with respect to a storage cell on either column of said first pair of adjacent columns.
5. The ROM circuit as set forth in claim 1 , wherein said shared source line and said shared bit line alternate across said array.
6. The ROM circuit as set forth in claim 1 , wherein a storage cell is provided with a diffusion area between its drain and source terminals for programming a logic value thereat.
7. The ROM circuit as set forth in claim 6 , wherein said logic value comprises a binary 0.
8. The ROM circuit as set forth in claim 1 , wherein a diffusion area is withheld between drain and source terminals of a storage cell for programming a logic value thereat.
9. The ROM circuit as set forth in claim 8 , wherein said logic value comprises a binary 1.
10. The ROM circuit as set forth in claim 8 , wherein said storage cell is disposed on a particular column of said first pair of adjacent columns and said source terminal of said storage cell is provided with a source diffusion extension, if said storage cell is located next to another storage cell on said particular column having said logic value.
11. The ROM circuit as set forth in claim 8 , wherein said storage cell is disposed on a particular column of said second pair of adjacent columns and said drain terminal of said storage cell is provided with a drain diffusion extension, if said storage cell is located next to another storage cell on said particular column having said logic value.
12. The ROM circuit as set forth in claim 1 , wherein said first and second predetermined levels comprise voltages that are substantially equal.
13. The ROM circuit as set forth in claim 1 , wherein said array comprises equal number of said rows and said columns.
14. A memory compiler for compiling at least one Read-Only Memory (ROM) instance, comprising:
a code portion for providing a plurality of ROM storage cells organized as an array of rows and columns;
a code portion for providing a shared source line associated with a first pair of adjacent columns, said shared source line being maintained at a first predetermined level, wherein source terminals of storage cells in said adjacent columns of said first pair are electrically coupled to said shared source line; and
a code portion for providing a shared bit line associated with a second pair of adjacent columns, said shared bit line being maintained at a second predetermined level, wherein drain terminals of storage cells in said adjacent columns of said second pair are electrically coupled to said shared bit line.
15. The ROM memory compiler for compiling at least one ROM memory instance as set forth in claim 14 , wherein said first predetermined level comprises a voltage level to which said shared source line is precharged.
16. The ROM memory compiler for compiling at least one ROM memory instance as set forth in claim 14 , wherein said second predetermined level comprises a voltage level to which said shared bit line is precharged.
17. The ROM memory compiler for compiling at least one ROM memory instance as set forth in claim 14 , wherein said shared source line is operable to be driven low upon commencing a memory access operation with respect to a storage cell on either column of said first pair of adjacent columns.
18. The ROM memory compiler for compiling at least one ROM memory instance as set forth in claim 14 , wherein said shared source line and said shared bit line alternate across said array.
19. The ROM memory compiler for compiling at least one ROM memory instance as set forth in claim 14 , wherein a storage cell is provided with a diffusion area between its drain and source terminals for programming a logic value thereat.
20. The ROM memory compiler for compiling at least one ROM memory instance as set forth in claim 19 , wherein said logic value comprises a binary 0.
21. The ROM memory compiler for compiling at least one ROM memory instance as set forth in claim 14 , wherein a diffusion area is withheld between drain and source terminals of a storage cell for programming a logic value thereat.
22. The ROM memory compiler for compiling at least one ROM memory instance as set forth in claim 21 , wherein said logic value comprises a binary 1.
23. The ROM memory compiler for compiling at least one ROM memory instance as set forth in claim 21 , wherein said storage cell is disposed on a particular column of said first pair of adjacent columns and said source terminal of said storage cell is provided with a source diffusion extension, if said storage cell is located next to another storage cell on said particular column having said logic value.
24. The ROM memory compiler for compiling at least one ROM memory instance as set forth in claim 21 , wherein said storage cell is disposed on a particular column of said second pair of adjacent columns and said drain terminal of said storage cell is provided with a drain diffusion extension, if said storage cell is located next to another storage cell on said particular column having said logic value.
25. The ROM memory compiler for compiling at least one ROM memory instance as set forth in claim 14 , wherein said first and second predetermined levels comprise voltages that are substantially equal.
26. The ROM memory compiler for compiling at least one ROM memory instance as set forth in claim 14 , wherein said array comprises equal number of said rows and said columns.