Low leakage ROM architecture
View Patent ↗Read only memory (ROM) with minimum leakage is provided. The ROM includes a read only memory array. The read only memory array includes a first transistor, wherein a drain, a source, a gate, and a bulk of the first transistor is electrically connected to a logic zero in the idle state for ensuring zero junction and sub-threshold leakage current. Another ROM includes a first transistor comprising a gate, electrically connected to a word line to provide a read signal, a drain, electrically connected to a main bit line through a second transistor. The second transistor includes a gate, electrically connected to a first decoding circuit, a drain, electrically connected to the main bit line. A first reference bit line is electrically connected to a drain of a third transistor, wherein gate of the third transistor is electrically connected to a second decoding circuit for generating a stop read signal. A second reference bit line, electrically connected to the first decoding circuit through a first sensing unit for generating a stop pre-charge signal. Further, a reference word line is electrically connected to a gate of a fourth transistor.
1. A read only memory comprising:
a first transistor comprising a gate, a drain, and a source, the gate of the first transistor directly connected to a word line to provide a read signal, the drain of the first transistor directly connected to a main bit line through a second transistor, and the source of the first transistor is electrically grounded;
the second transistor comprising a gate, a drain and a source, the gate of the second transistor is directly connected to a first decoding circuit, the drain of the second transistor is directly connected to the main bit line, and the source of the second transistor is directly connected to a power supply;
a first reference bit line directly connected to a drain of a third transistor, wherein gate of the third transistor is directly connected to a second decoding circuit to generate a stop read signal;
a second reference bit line directly connected to the first decoding circuit through a first sensing unit for generating a stop pre-charge signal; and
a reference word line directly connected to a gate of a fourth transistor.
2. The read only memory of claim 1 , wherein a source of the third transistor is electrically connected to the power supply.
3. The read only memory of claim 1 , wherein a source of the fourth transistor is electrically grounded.
4. The read only memory of claim 1 , further comprising a fifth transistor, wherein the fifth transistor comprises a gate, a drain and a source, the gate electrically connected to a clock, the drain electrically connected to the second reference bit line, and the source electrically connected to the power supply.
5. The read only memory of claim 4 , wherein the clock is electrically connected to the first decoding circuit and the second decoding circuit.
6. The read only memory of claim 1 further comprising a second sensing unit for sensing charging and discharging of the main bit line.
7. The read only memory of claim 6 , wherein the second sensing unit comprises an inverter circuit.
8. The read only memory of claim 1 further comprising a third sensing circuit for sensing charging and discharging of the second reference bit line.
9. The read only memory of claim 1 further comprising an output driver to drive the output of the second sensing unit.
10. A method for minimizing leakage current in a read only memory, the method comprising:
connecting a drain of a first transistor to a main bit line through a second transistor;
pre-charging the main bit line through the second transistor, a first reference bit line and a second reference bit line, wherein the second reference bit line provides a stop pre-charge signal;
connecting a gate of the first transistor directly to a word line;
connecting a gate of a fourth transistor directly to a reference word line;
providing a read signal to the gate of the first transistor through the word line and to the gate of the fourth transistor through the reference word line; and
discharging the first reference bit line through a third sensing unit to provide a stop read signal to the main bit line.
11. The method of claim 10 wherein the stop-precharge signal is provided through a first decoding circuit that receives a clocking signal and an address.
12. The method of claim 10 wherein the stop-read signal is provided through a second decoding circuit that receives the clocking signal and the stop-precharge signal.
13. The method of claim 10 wherein the stop-precharge signal is provided through a sense unit electrically connected to a transistor that receives the clocking signal.