Native high-voltage n-channel LDMOSFET in standard logic CMOS
View Patent ↗A native high-voltage n-channel LDMOSFET includes a p− doped substrate, a first n+ doped region disposed in the p− doped substrate, a source terminal coupled to the first n+ doped region, an n− well disposed in the substrate, a second n+ doped region disposed in the n− well, a drain terminal coupled to the second n+ doped region, a p+ doped region disposed in the substrate, a body terminal coupled to the p+ doped region, a dielectric layer disposed over the p− doped substrate and a portion of the n− well, a first trench disposed in the n− well, the trench filled with a dielectric material that is in contact with the dielectric layer, a second trench disposed at least partially in the n− well, the second trench filled with a dielectric material and isolating the second n+ region from the p+ region, and a gate partially or fully reversely doped with p+ implant (or an equivalent technique) and disposed over the dielectric layer and a portion of the first trench.
1. A high-voltage n-channel MOSFET, comprising:
a native p− doped substrate having no p− well;
a first n+ doped source region disposed in said substrate;
a source terminal coupled to said first n+ doped region;
an n− well disposed in said substrate;
a second n+ doped drain region disposed in said n− well;
a drain terminal coupled to said second n+ doped region;
a channel region disposed between said source region and said drain region;
a p+ doped region disposed in said substrate;
a body terminal coupled to said p+ doped region;
a p− substrate/n− well junction region disposed at the interface of said p− substrate and said n− well;
a dielectric layer disposed over said channel region;
a first isolator disposed in said n− well, said isolator including a dielectric material that is in contact with said dielectric layer;
a second isolator disposed at least partially in said n− well, said second isolator including a dielectric material and isolating said second n+ region from said p+ region; and
a gate disposed over said dielectric layer and a portion of said first isolator, said gate comprising at least a first region of p+ doped semiconductor material and a second region of a different material contiguous with said first region of p+ doped semiconductor material.
2. The high-voltage n-channel MOSFET of claim 1 , wherein said p+ doped semiconductor material is p+ doped polysilicon.
3. The high-voltage n-channel MOSFET of claim 1 , wherein said gate comprises a layer having a region of p+ doped semiconductor layer surrounded by a first region of n+ doped semiconductor and a second region of n+ doped semiconductor.
4. The high-voltage n-channel MOSFET of claim 1 , wherein said gate comprises metal.
5. The high-voltage n-channel MOSFET of claim 1 , wherein said dielectric material is silicon dioxide.
6. The high-voltage n-channel MOSFET of claim 1 , wherein said isolators are formed with an STI process.
7. The high-voltage n-channel MOSFET of claim 1 , wherein said isolators are formed with a LOCOS process.
8. The high-voltage n-channel MOSFET of claim 1 , wherein:
the MOSFET is fabricated using a process technology providing an MFS (Minimum Feature Size) of no greater than 0.18 microns.
9. The high-voltage n-channel MOSFET of claim 8 , wherein:
the isolators are fabricated using STI.
10. The high-voltage n-channel MOSFET of claim 9 , wherein:
a length of a dimension Lw of a region of lateral diffusion under the gate is greater than or equal to 0.0 microns;
a length of a dimension Lc of the channel is greater than or equal to 0.7 microns;
a length of a dimension Ldp corresponding to the width of the first isolator is greater than or equal to 0.8 microns; and
a length of a dimension Lo of a region extending from an end of the channel to an end of the gate is greater than or equal to 0.4 microns.
11. The high-voltage n-channel MOSFET of claim 8 , wherein:
the isolators are fabricated using LOCOS.
12. The high-voltage n-channel MOSFET of claim 11 , wherein:
a length of a dimension Lw of a region of lateral diffusion under the gate is greater than or equal to 0.2 microns;
a length of a dimension Lc of the channel is greater than or equal to 0.7 microns;
a length of a dimension Ldp corresponding to the width of the first isolator is greater than or equal to 0.8 microns; and
a length of a dimension Lo of a region extending from an end of the channel to an end of the gate is greater than or equal to 0.4 microns.
13. A high-voltage n-channel MOSFET, comprising:
a native p− doped substrate having no p− well;
a first n+ doped source region disposed in said p− doped substrate;
a source terminal coupled to said first n+ doped source region;
an n− well disposed in said substrate;
a second n+ doped drain region disposed in said n− well;
a drain terminal coupled to said second n+ doped region;
a channel region disposed between said source region and said drain region;
a p+ doped region disposed in said substrate;
a body terminal coupled to said p+ doped region;
a junction region formed at an interface of p− substrate material and n− well material under said channel region;
a dielectric layer disposed over said channel region;
a first isolator disposed in said n− well, said isolator including a dielectric material that is in contact with said dielectric layer;
a second isolator disposed at least partially in said n− well, said second isolator including a dielectric material and isolating said second n+ region from said p+ region; and
a gate disposed over at least a portion of said channel region, said gate comprising a layer having a first region of p+ doped semiconductor material and a second region of a different material contiguous with the first region of p+ doped semiconductor material.
14. The high-voltage n-channel MOSFET of claim 13 , wherein said p+ doped semiconductor material comprises polysilicon.
15. The high-voltage n-channel MOSFET of claim 13 , wherein said second region comprises n+ doped semiconductor material.
16. The high-voltage n-channel MOSFET of claim 13 , wherein said second region comprises metal.
17. The high-voltage n-channel MOSFET of claim 13 , wherein said dielectric material is silicon dioxide.
18. The high-voltage n-channel MOSFET of claim 13 , wherein said isolators are formed with an STI process.
19. The high-voltage n-channel MOSFET of claim 13 , wherein said isolators are formed with a LOCOS process.
20. The high-voltage n-channel MOSFET of claim 13 , wherein:
the MOSFET is fabricated using a process technology providing an MFS (Minimum Feature Size) of no greater than 0.18 microns.
21. The high-voltage n-channel MOSFET of claim 20 , wherein:
the isolators are fabricated using STI.
22. The high-voltage n-channel MOSFET of claim 21 , wherein:
a length of a dimension Lw of a region of lateral diffusion under the gate is greater than or equal to 0.0 microns;
a length of a dimension Lc of the channel is greater than or equal to 0.7 microns;
a length of a dimension Ldp corresponding to the width of the first isolator is greater than or equal to 0.8 microns; and
a length of a dimension Lo of a region extending from an end of the channel to an end of the gate is greater than or equal to 0.4 microns.
23. The high-voltage n-channel MOSFET of claim 20 , wherein:
the isolators are fabricated using LOCOS.
24. The high-voltage n-channel MOSFET of claim 23 , wherein:
a length of a dimension Lw of a region of lateral diffusion under the gate is greater than or equal to 0.2 microns;
a length of a dimension Lc of the channel is greater than or equal to 0.7 microns;
a length of a dimension Ldp corresponding to the width of the first isolator is greater than or equal to 0.8 microns; and
a length of a dimension Lo of a region extending from an end of the channel to an end of the gate is greater than or equal to 0.4 micron.